Home
last modified time | relevance | path

Searched +full:pci +full:- +full:ep +full:- +full:bus (Results 1 – 25 of 116) sorted by relevance

12345

/linux/drivers/pci/controller/dwc/
H A Dpci-exynos.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2013-2020 Samsung Electronics Co., Ltd.
17 #include <linux/pci.h>
24 #include "pcie-designware.h"
26 #define to_exynos_pcie(x) dev_get_drvdata((x)->dev)
55 struct dw_pcie pci; member
71 static void exynos_pcie_sideband_dbi_w_mode(struct exynos_pcie *ep, bool on) in exynos_pcie_sideband_dbi_w_mode() argument
73 struct dw_pcie *pci = &ep->pci; in exynos_pcie_sideband_dbi_w_mode() local
76 val = exynos_pcie_readl(pci->elbi_base, PCIE_ELBI_SLV_AWMISC); in exynos_pcie_sideband_dbi_w_mode()
81 exynos_pcie_writel(pci->elbi_base, val, PCIE_ELBI_SLV_AWMISC); in exynos_pcie_sideband_dbi_w_mode()
[all …]
H A Dpci-keystone.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2013-2014 Texas Instruments., Ltd.
8 * Author: Murali Karicheri <m-karicheri2@ti.com>
9 * Implementation based on pci-exynos.c and pcie-designware.c
30 #include "../../pci.h"
31 #include "pcie-designware.h"
59 #define PCIE_LEGACY_IRQ_ENABLE_SET(n) (0x188 + (0x10 * ((n) - 1)))
60 #define PCIE_LEGACY_IRQ_ENABLE_CLR(n) (0x18c + (0x10 * ((n) - 1)))
84 #define ERR_NONFATAL BIT(2) /* Non-fatal error */
99 #define EP 0x0 macro
[all …]
H A Dpcie-designware.h1 /* SPDX-License-Identifier: GPL-2.0 */
17 #include <linux/dma-mapping.h>
22 #include <linux/pci.h>
23 #include <linux/pci-ecam.h>
26 #include <linux/pci-epc.h>
27 #include <linux/pci-epf.h>
29 #include "../../pci.h"
31 /* DWC PCIe IP-core versions (native support since v4.70a) */
41 ((_pci)->version _op DW_PCIE_VER_ ## _ver)
61 test_bit(DW_PCIE_CAP_ ## _cap, &(_pci)->caps)
[all …]
H A Dpcie-dw-rockchip.c1 // SPDX-License-Identifier: GPL-2.0
6 * http://www.rock-chips.com
8 * Author: Simon Xue <xxm@rock-chips.com>
26 #include "../../pci.h"
27 #include "pcie-designware.h"
34 #define to_rockchip_pcie(x) dev_get_drvdata((x)->dev)
78 struct dw_pcie pci; member
97 return readl_relaxed(rockchip->apb_base + reg); in rockchip_pcie_readl_apb()
103 writel_relaxed(val, rockchip->apb_base + reg); in rockchip_pcie_writel_apb()
117 generic_handle_domain_irq(rockchip->irq_domain, hwirq); in rockchip_pcie_intx_handler()
[all …]
H A Dpci-imx6.c1 // SPDX-License-Identifier: GPL-2.0
17 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
18 #include <linux/mfd/syscon/imx7-iomuxc-gpr.h>
22 #include <linux/pci.h>
36 #include "../../pci.h"
37 #include "pcie-designware.h"
82 #define to_imx_pcie(x) dev_get_drvdata((x)->dev)
118 #define imx_check_flag(pci, val) (pci->drvdata->flags & val) argument
148 struct dw_pcie *pci; member
183 /* PCIe Port Logic registers (memory-mapped) */
[all …]
H A Dpcie-tegra194.c1 // SPDX-License-Identifier: GPL-2.0+
7 * Copyright (C) 2019-2022 NVIDIA Corporation.
24 #include <linux/pci.h>
33 #include "pcie-designware.h"
35 #include <soc/tegra/bpmp-abi.h>
36 #include "../../pci.h"
248 struct dw_pcie pci; member
288 static inline struct tegra_pcie_dw *to_tegra_pcie(struct dw_pcie *pci) in to_tegra_pcie() argument
290 return container_of(pci, struct tegra_pcie_dw, pci); in to_tegra_pcie()
296 writel_relaxed(value, pcie->appl_base + reg); in appl_writel()
[all …]
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
3 menu "DesignWare-based PCIe controllers"
4 depends on PCI
39 required only for DT-based platforms. ACPI platforms with the
50 DesignWare IP and therefore the driver re-uses the DesignWare
59 Say Y here if you want to enable PCI controller support on Amlogic
60 SoCs. The PCI controller on Amlogic is based on DesignWare hardware
61 and therefore the driver re-uses the DesignWare core functions to
68 bool "Axis ARTPEC-6 PCIe controller (host mode)"
74 Enables support for the PCIe controller in the ARTPEC-6 SoC to work in
[all …]
H A Dpcie-qcom-ep.c1 // SPDX-License-Identifier: GPL-2.0
26 #include "../../pci.h"
27 #include "pcie-designware.h"
28 #include "pcie-qcom-common.h"
157 #define to_pcie_ep(x) dev_get_drvdata((x)->dev)
167 * struct qcom_pcie_ep_cfg - Per SoC config struct
179 * struct qcom_pcie_ep - Qualcomm PCIe Endpoint Controller
180 * @pci: Designware PCIe controller struct
195 * @cfg: PCIe EP config struct
201 struct dw_pcie pci; member
[all …]
H A Dpcie-designware-ep.c1 // SPDX-License-Identifier: GPL-2.0
14 #include "pcie-designware.h"
15 #include <linux/pci-epc.h>
16 #include <linux/pci-epf.h>
19 * dw_pcie_ep_get_func_from_ep - Get the struct dw_pcie_ep_func corresponding to
21 * @ep: DWC EP device
27 dw_pcie_ep_get_func_from_ep(struct dw_pcie_ep *ep, u8 func_no) in dw_pcie_ep_get_func_from_ep() argument
31 list_for_each_entry(ep_func, &ep->func_list, list) { in dw_pcie_ep_get_func_from_ep()
32 if (ep_func->func_no == func_no) in dw_pcie_ep_get_func_from_ep()
39 static void __dw_pcie_ep_reset_bar(struct dw_pcie *pci, u8 func_no, in __dw_pcie_ep_reset_bar() argument
[all …]
/linux/drivers/acpi/
H A Dviot.c1 // SPDX-License-Identifier: GPL-2.0
6 * para-virtual IOMMUs and the endpoints they manage. The OS uses it to
16 * hasn't yet been initialized, VIOT returns -EPROBE_DEFER to postpone probing
24 #include <linux/pci.h>
37 /* PCI range */
62 max_t(size_t, sizeof(*viot), viot->node_offset)); in viot_check_bounds()
63 end = ACPI_ADD_PTR(struct acpi_viot_header, viot, viot->header.length); in viot_check_bounds()
68 return -EOVERFLOW; in viot_check_bounds()
70 if (hdr->length < sizeof(*hdr)) { in viot_check_bounds()
72 return -EINVAL; in viot_check_bounds()
[all …]
/linux/Documentation/PCI/endpoint/
H A Dpci-vntb-function.rst1 .. SPDX-License-Identifier: GPL-2.0
4 PCI vNTB Function
9 The difference between PCI NTB function and PCI vNTB function is
11 PCI NTB function need at two endpoint instances and connect HOST1
14 PCI vNTB function only use one host and one endpoint(EP), use NTB
15 connect EP and PCI host
17 .. code-block:: text
20 +------------+ +---------------------------------------+
22 +------------+ | +--------------+
25 +------------+ | +--------------+
[all …]
H A Dpci-ntb-howto.rst1 .. SPDX-License-Identifier: GPL-2.0
4 PCI Non-Transparent Bridge (NTB) Endpoint Function (EPF) User Guide
9 This document is a guide to help users use pci-epf-ntb function driver
11 be followed in the host side and EP side is given below. For the hardware
13 Documentation/PCI/endpoint/pci-ntb-function.rst
19 ---------------------------
27 2900000.pcie-ep 2910000.pcie-ep
32 2900000.pcie-ep 2910000.pcie-ep
36 -------------------------
40 # ls /sys/bus/pci-epf/drivers
[all …]
H A Dpci-vntb-howto.rst1 .. SPDX-License-Identifier: GPL-2.0
4 PCI Non-Transparent Bridge (NTB) Endpoint Function (EPF) User Guide
9 This document is a guide to help users use pci-epf-vntb function driver
11 be followed in the host side and EP side is given below. For the hardware
13 Documentation/PCI/endpoint/pci-vntb-function.rst
19 ---------------------------
32 -------------------------
36 # ls /sys/bus/pci-epf/drivers
45 Creating pci-epf-vntb Device
46 ----------------------------
[all …]
/linux/drivers/pci/controller/
H A Dpcie-rockchip-ep.c1 // SPDX-License-Identifier: GPL-2.0+
7 * Author: Shawn Lin <shawn.lin@rock-chips.com>
8 * Simon Xue <xxm@rock-chips.com>
18 #include <linux/pci-epc.h>
20 #include <linux/pci-epf.h>
24 #include "pcie-rockchip.h"
27 * struct rockchip_pcie_ep - private data for PCIe endpoint controller driver
29 * @epc: PCI EPC device
32 * @ob_addr: base addresses in the AXI bus where the outbound regions start
33 * @irq_phys_addr: base address on the AXI bus where the MSI/INTX IRQ
[all …]
/linux/Documentation/devicetree/bindings/misc/
H A Dpci1de4,1.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RaspberryPi RP1 MFD PCI device
10 - A. della Porta <andrea.porta@suse.com>
13 The RaspberryPi RP1 is a PCI multi function device containing
16 The peripherals are accessed by addressing the PCI BAR1 region.
19 - $ref: /schemas/pci/pci-ep-bus.yaml
26 - const: pci1de4,1
28 '#interrupt-cells':
[all …]
/linux/Documentation/devicetree/bindings/pci/
H A Dst,stm32-pcie-ep.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/st,stm32-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Christian Bruel <christian.bruel@foss.st.com>
16 - $ref: /schemas/pci/snps,dw-pcie-ep.yaml#
17 - $ref: /schemas/pci/st,stm32-pcie-common.yaml#
21 const: st,stm32mp25-pcie-ep
25 - description: Data Bus Interface (DBI) registers.
26 - description: Data Bus Interface (DBI) shadow registers.
[all …]
H A Drockchip-dw-pcie-ep.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/rockchip-dw-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Niklas Cassel <cassel@kernel.org>
15 snps,dw-pcie-ep.yaml.
18 - $ref: /schemas/pci/snps,dw-pcie-ep.yaml#
19 - $ref: /schemas/pci/rockchip-dw-pcie-common.yaml#
24 - rockchip,rk3568-pcie-ep
25 - rockchip,rk3588-pcie-ep
[all …]
H A Dti,j721e-pci-ep.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: http://devicetree.org/schemas/pci/ti,j721e-pci-ep.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: TI J721E PCI EP (PCIe Wrapper)
11 - Kishon Vijay Abraham I <kishon@ti.com>
16 - const: ti,j721e-pcie-ep
17 - const: ti,j784s4-pcie-ep
18 - description: PCIe EP controller in AM64
[all …]
H A Dsnps,dw-pcie-ep.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pci/snps,dw-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jingoo Han <jingoohan1@gmail.com>
11 - Gustavo Pimentel <gustavo.pimentel@synopsys.com>
16 # Please create a separate DT-schema for your DWC PCIe Endpoint controller
17 # and make sure it's assigned with the vendor-specific compatible string.
21 const: snps,dw-pcie-ep
23 - compatible
[all …]
H A Dti-pci.txt1 TI PCI Controllers
4 - compatible: Should be "ti,dra7-pcie" for RC (deprecated)
5 Should be "ti,dra7-pcie-ep" for EP (deprecated)
6 Should be "ti,dra746-pcie-rc" for dra74x/dra76 in RC mode
7 Should be "ti,dra746-pcie-ep" for dra74x/dra76 in EP mode
8 Should be "ti,dra726-pcie-rc" for dra72x in RC mode
9 Should be "ti,dra726-pcie-ep" for dra72x in EP mode
10 - phys : list of PHY specifiers (used by generic PHY framework)
11 - phy-names : must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the
13 - ti,hwmods : Name of the hwmod associated to the pcie, "pcie<X>",
[all …]
H A Drockchip,rk3399-pcie-ep.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/rockchip,rk3399-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shawn Lin <shawn.lin@rock-chips.com>
13 - $ref: /schemas/pci/pci-ep.yaml#
14 - $ref: rockchip,rk3399-pcie-common.yaml#
18 const: rockchip,rk3399-pcie-ep
22 reg-names:
24 - const: apb-base
[all …]
H A Dcdns,cdns-pcie-ep.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/pci/cdns,cdns-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Cadence PCIe EP Controller
10 - Tom Joseph <tjoseph@cadence.com>
13 - $ref: cdns-pcie-ep.yaml#
17 const: cdns,cdns-pcie-ep
22 reg-names:
24 - const: reg
[all …]
H A Daxis,artpec6-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/pci/axis,artpec6-pcie.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Axis ARTPEC-6 PCIe host controller
11 - Jesper Nilsson <jesper.nilsson@axis.com>
21 - axis,artpec6-pcie
22 - axis,artpec6-pcie-ep
23 - axis,artpec7-pcie
24 - axis,artpec7-pcie-ep
[all …]
/linux/drivers/pci/endpoint/
H A Dpci-epf-core.c1 // SPDX-License-Identifier: GPL-2.0
3 * PCI Endpoint *Function* (EPF) library
10 #include <linux/dma-mapping.h>
14 #include <linux/pci-epc.h>
15 #include <linux/pci-epf.h>
16 #include <linux/pci-ep-cfs.h>
24 * pci_epf_unbind() - Notify the function driver that the binding between the
35 if (!epf->driver) { in pci_epf_unbind()
36 dev_WARN(&epf->dev, "epf device not bound to driver\n"); in pci_epf_unbind()
40 mutex_lock(&epf->lock); in pci_epf_unbind()
[all …]
/linux/drivers/pci/controller/cadence/
H A Dpci-j721e.c1 // SPDX-License-Identifier: GPL-2.0
3 * pci-j721e - PCIe controller driver for TI's J721E SoCs
5 * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com
10 #include <linux/clk-provider.h>
20 #include <linux/pci.h>
25 #include "../../pci.h"
26 #include "pcie-cadence.h"
85 return readl(pcie->user_cfg_base + offset); in j721e_pcie_user_readl()
91 writel(value, pcie->user_cfg_base + offset); in j721e_pcie_user_writel()
96 return readl(pcie->intd_cfg_base + offset); in j721e_pcie_intd_readl()
[all …]

12345