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/linux/Documentation/devicetree/bindings/clock/
H A Didt,versaclock5.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 clock generators providing from 3 to 12 output clocks.
16 - 5P49V5923:
17 0 -- OUT0_SEL_I2CB
18 1 -- OUT1
19 2 -- OUT2
21 - 5P49V5933:
22 0 -- OUT0_SEL_I2CB
[all …]
/linux/drivers/media/dvb-frontends/
H A Dm88ds3103.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
19 * enum m88ds3103_ts_mode - TS connection mode
20 * @M88DS3103_TS_SERIAL: TS output pin D0, normal
21 * @M88DS3103_TS_SERIAL_D7: TS output pin D7
34 * @M88DS3103_CLOCK_OUT_DISABLED: Clock output is disabled
35 * @M88DS3103_CLOCK_OUT_ENABLED: Clock output is enabled with crystal
37 * @M88DS3103_CLOCK_OUT_ENABLED_DIV2: Clock output is enabled with half
47 * struct m88ds3103_platform_data - Platform data for the m88ds3103 driver
52 * @ts_clk_pol: TS clk polarity. 1-active at falling edge; 0-active at rising
57 * @clk_out: Clock output.
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/linux/drivers/media/platform/ti/omap3isp/
H A Disppreview.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * TI OMAP3 ISP driver - Preview module
26 { /* RGB-RGB Matrix */
38 {-38, -75, 112},
39 {112, -94 , -18}
85 * -------------------------------------------------------------
125 * Default Gamma Correction Table - All components
146 * preview_config_luma_enhancement - Configure the Luminance Enhancement table
153 const struct omap3isp_prev_luma *yt = &params->luma; in preview_config_luma_enhancement()
159 isp_reg_writel(isp, yt->table[i], in preview_config_luma_enhancement()
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H A Domap3isp.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * TI OMAP3 ISP - Bus Configuration
25 * struct isp_parallel_cfg - Parallel interface configuration
27 * 0 - CAMEXT[13:0] -> CAM[13:0]
28 * 2 - CAMEXT[13:2] -> CAM[11:0]
29 * 4 - CAMEXT[13:4] -> CAM[9:0]
30 * 6 - CAMEXT[13:6] -> CAM[7:0]
32 * 0 - Sample on rising edge, 1 - Sample on falling edge
34 * 0 - Active high, 1 - Active low
36 * 0 - Active high, 1 - Active low
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/linux/Documentation/trace/coresight/
H A Dcoresight-ect.rst1 .. SPDX-License-Identifier: GPL-2.0
11 --------------------
14 individual input and output hardware signals known as triggers to and from
21 0 C 0----------->: : +======>(other CTI channel IO)
22 0 P 0<-----------: : v
24 0000000 : CTI :<=========>*CTM*<====>: CTI :---+
25 ####### in_trigs : : (id 0-3) ***** ::::::: v
26 # ETM #----------->: : ^ #######
27 # #<-----------: : +---# ETR #
31 channels. When an input trigger becomes active, the attached channel will
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/linux/drivers/watchdog/
H A Dwd501p.h1 /* SPDX-License-Identifier: GPL-1.0+ */
25 #define WDT_BUZZER (io+6) /* PCI only: rd=disable, wr=enable */
31 /* inverted opto isolated reset output: */
32 #define WDT_OPTONOTRST (io+13) /* wr=enable, rd=disable */
33 /* opto isolated reset output: */
34 #define WDT_OPTORST (io+14) /* wr=enable, rd=disable */
36 #define WDT_PROGOUT (io+15) /* wr=enable, rd=disable */
39 #define WDC_SR_WCCR 1 /* Active low */ /* X X X */
40 #define WDC_SR_TGOOD 2 /* X X - */
43 #define WDC_SR_FANGOOD 16 /* X - - */
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/linux/Documentation/devicetree/bindings/media/i2c/
H A Daptina,mt9v111.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jacopo Mondi <jacopo@jmondi.org>
13 The Aptina MT9V111 is a 1/4-Inch VGA-format digital image sensor with a core
16 The sensor has an active pixel array of 640x480 pixels and can output a number
17 of image resolutions and formats controllable through a simple two-wires
30 enable-gpios:
31 description: Enable signal, pin name "OE#". Active low.
34 standby-gpios:
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H A Dtoshiba,tc358746.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marco Felsch <kernel@pengutronix.de>
12 description: |-
13 The Toshiba TC358746 converts a parallel video stream into a MIPI CSI-2
14 stream. The direction can be either parallel-in -> csi-out or csi-in ->
15 parallel-out The chip is programmable through I2C and SPI but the SPI
16 interface is only supported in parallel-in -> csi-out mode.
19 parallel-in -> csi-out path.
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/linux/arch/arm64/boot/dts/mediatek/
H A Dmt8186-corsola-steelix.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 /dts-v1/;
7 #include "mt8186-corsola.dtsi"
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
12 pp1000_edpbrdg: regulator-pp1000-edpbrdg {
13 compatible = "regulator-fixed";
14 regulator-name = "pp1000_edpbrdg";
15 pinctrl-names = "default";
16 pinctrl-0 = <&en_pp1000_edpbrdg>;
[all …]
H A Dmt8390-genio-common.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
4 * Author: Chris Chen <chris-qj.chen@mediatek.com>
9 * Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/input/input.h>
16 #include <dt-bindings/interrupt-controller/irq.h>
17 #include <dt-bindings/pinctrl/mediatek,mt8188-pinfunc.h>
18 #include <dt-bindings/regulator/mediatek,mt6360-regulator.h>
19 #include <dt-bindings/spmi/spmi.h>
20 #include <dt-bindings/usb/pd.h>
[all …]
H A Dmt8192-asurada.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 /dts-v1/;
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/spmi/spmi.h>
25 stdout-path = "serial0:115200n8";
33 backlight_lcd0: backlight-lcd0 {
34 compatible = "pwm-backlight";
36 power-supply = <&ppvar_sys>;
37 enable-gpios = <&pio 152 0>;
38 brightness-levels = <0 1023>;
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/linux/Documentation/devicetree/bindings/power/supply/
H A Dmaxim,max8903.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sebastian Reichel <sre@kernel.org>
13 - $ref: power-supply.yaml#
19 dok-gpios:
21 description: Valid DC power has been detected (active low, input)
23 uok-gpios:
25 description: Valid USB power has been detected (active low, input)
27 cen-gpios:
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/linux/Documentation/devicetree/bindings/regulator/
H A Drichtek,rtmv20-regulator.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/regulator/richtek,rtmv20-regulator.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - ChiYuan Huang <cy_huang@richtek.com>
15 (Enable/Fail), Enable pin to turn chip on, and Fail pin as fault indication.
18 supply, vsync input from IR camera, and fsin1/fsin2 output for the optional.
27 wakeup-source: true
32 enable-gpios:
33 description: A connection of the 'enable' gpio line.
[all …]
H A Dti,tps65132.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TI TPS65132 Dual Output Power Regulators
10 - devicetree@vger.kernel.org
21 - ti,tps65132
26 vin-supply: true
37 enable-gpios:
40 GPIO specifier to enable the GPIO control (on/off) for regulator.
42 active-discharge-gpios:
[all …]
H A Dgpio-regulator.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/regulator/gpio-regulator.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Liam Girdwood <lgirdwood@gmail.com>
11 - Mark Brown <broonie@kernel.org>
18 - $ref: regulator.yaml#
22 const: regulator-gpio
24 regulator-name: true
26 enable-gpios:
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/linux/drivers/video/fbdev/
H A Dpxa3xx-regs.h1 /* SPDX-License-Identifier: GPL-2.0 */
57 #define LCCR0_ENB (1 << 0) /* LCD Controller enable */
69 #define LCCR0_PAS (1 << 7) /* Passive/Active display Select */
71 #define LCCR0_Act (LCCR0_PAS*1) /* Active display (TFT) */
73 #define LCCR0_4PixMono (LCCR0_DPD*0) /* 4-Pixel/clock Monochrome display */
74 #define LCCR0_8PixMono (LCCR0_DPD*1) /* 8-Pixel/clock Monochrome display */
80 #define LCCR0_OUM (1 << 21) /* Output FIFO underrun mask */
90 #define LCCR1_PPL Fld (10, 0) /* Pixels Per Line - 1 */
91 #define LCCR1_DisWdth(Pixel) (((Pixel) - 1) << FShft (LCCR1_PPL))
94 #define LCCR1_HorSnchWdth(Tpix) (((Tpix) - 1) << FShft (LCCR1_HSW))
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/linux/Documentation/trace/
H A Dintel_th.rst1 .. SPDX-License-Identifier: GPL-2.0
8 --------
11 switch and output trace data from multiple hardware and software
12 sources over several types of trace output ports encoded in System
23 - Software Trace Hub (STH), trace source, which is a System Trace
25 - Memory Storage Unit (MSU), trace output, which allows storing
26 trace hub output in system memory,
27 - Parallel Trace Interface output (PTI), trace output to an external
29 - Global Trace Hub (GTH), which is a switch and a central component
32 Common attributes for output devices are described in
[all …]
/linux/drivers/net/phy/
H A Ddp83640_reg.h1 /* SPDX-License-Identifier: GPL-2.0 */
20 #define PTP_TXTS 0x001c /* PTP Transmit Timestamp Register, in four 16-bit reads */
21 #define PTP_RXTS 0x001d /* PTP Receive Timestamp Register, in six? 16-bit reads */
40 #define PTP_COC 0x0014 /* PTP Clock Output Control Register */
54 #define BC_WRITE (1<<11) /* Broadcast Write Enable */
60 #define TRIG_EN (1<<8) /* Enable PTP Trigger */
66 #define PTP_ENABLE (1<<2) /* Enable PTP Clock */
75 #define TXTS_IE (1<<3) /* Transmit Timestamp Interrupt Enable */
76 #define RXTS_IE (1<<2) /* Receive Timestamp Interrupt Enable */
77 #define TRIG_IE (1<<1) /* Trigger Interrupt Enable */
[all …]
/linux/Documentation/gpu/
H A Dzynqmp.rst1 .. SPDX-License-Identifier: GPL-2.0+
7 This subsystem handles DisplayPort video and audio output on the ZynqMP. It
8 supports in-memory framebuffers with the DisplayPort DMA controller
9 (xilinx-dpdma), as well as "live" video and audio from the programmable logic
15 -------
18 though debugfs. The following files in /sys/kernel/debug/dri/X/DP-1/test/
21 active:
24 active/inactive will re-activate/re-deactivate test mode. When test
27 activated. When test mode is active, changes made to other files will
34 Enable/disable clock downspreading (spread-spectrum clocking) by
[all …]
/linux/arch/arm/mach-pxa/
H A Dpxa27x-udc.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 #include "pxa-regs.h"
12 #define UDCCR_OEN (1 << 31) /* On-the-Go Enable */
13 #define UDCCR_AALTHNP (1 << 30) /* A-device Alternate Host Negotiation
15 #define UDCCR_AHNP (1 << 29) /* A-device Host Negotiation Protocol
17 #define UDCCR_BHNP (1 << 28) /* B-device Host Negotiation Protocol
18 Enable */
19 #define UDCCR_DWRE (1 << 16) /* Device Remote Wake-up Enable */
20 #define UDCCR_ACN (0x03 << 11) /* Active UDC configuration Number */
22 #define UDCCR_AIN (0x07 << 8) /* Active UDC interface Number */
[all …]
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6q-apalis-ixora-v1.2.dts1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
3 * Copyright 2014-2022 Toradex
8 /dts-v1/;
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/input/input.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
14 #include "imx6qdl-apalis.dtsi"
18 compatible = "toradex,apalis_imx6q-ixora-v1.2", "toradex,apalis_imx6q",
30 stdout-path = "serial0:115200n8";
34 compatible = "gpio-leds";
[all …]
/linux/drivers/usb/gadget/udc/
H A Dpxa27x_udc.h1 // SPDX-License-Identifier: GPL-2.0+
4 * Intel PXA27x on-chip full speed USB device controller
28 #define UDCOTGICR 0x0018 /* UDC On-The-Go interrupt control */
29 #define UP2OCR 0x0020 /* USB Port 2 Output Control register */
30 #define UP3OCR 0x0024 /* USB Port 3 Output Control register */
36 #define UDCCR_OEN (1 << 31) /* On-the-Go Enable */
37 #define UDCCR_AALTHNP (1 << 30) /* A-device Alternate Host Negotiation
39 #define UDCCR_AHNP (1 << 29) /* A-device Host Negotiation Protocol
41 #define UDCCR_BHNP (1 << 28) /* B-device Host Negotiation Protocol
42 Enable */
[all …]
/linux/drivers/scsi/
H A Dfdomain.h1 /* SPDX-License-Identifier: GPL-2.0 */
20 #define BSTAT_IO BIT(2) /* Input/Output */
31 #define BCTL_IO BIT(4) /* Input/Output */
34 #define BCTL_BUSEN BIT(7) /* Enable bus drivers */
36 #define ASTAT_IRQ BIT(0) /* Interrupt active */
50 #define REG_FSTAT 3 /* R: Adapter Status 2 (FIFO) - (@) */
51 #define FSTAT_ONOTEMPTY BIT(0) /* Output FIFO not empty */
57 #define MCTL_ACTDEASS BIT(4) /* Active deassert of REQ and ACK */
58 #define MCTL_TARGET BIT(5) /* Enable target mode */
59 #define MCTL_FASTSYNC BIT(6) /* Enable Fast Synchronous */
[all …]
/linux/arch/arm64/boot/dts/rockchip/
H A Drk3588-firefly-itx-3588j.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 /dts-v1/;
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/input/input.h>
7 #include <dt-bindings/leds/common.h>
8 #include <dt-bindings/pinctrl/rockchip.h>
9 #include <dt-bindings/pwm/pwm.h>
10 #include <dt-bindings/soc/rockchip,vop2.h>
11 #include "dt-bindings/usb/pd.h"
13 #include "rk3588-firefly-core-3588j.dtsi"
[all …]
/linux/Documentation/devicetree/bindings/memory-controllers/
H A Darm,pl172.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/arm,pl172.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Li <Frank.Li@nxp.com>
18 - arm,pl172
19 - arm,pl175
20 - arm,pl176
22 - compatible
27 - enum:
[all …]

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