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/linux/drivers/net/ethernet/mellanox/mlx4/
H A Dreset.c5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
8 * COPYING in the main directory of this source tree, or the
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
[all …]
/linux/Documentation/devicetree/bindings/reset/
H A Dzynq-reset.txt1 Xilinx Zynq Reset Manager
3 The Zynq AP-SoC has several different resets.
5 See Chapter 26 of the Zynq TRM (UG585) for more information about Zynq resets.
8 - compatible: "xlnx,zynq-reset"
9 - reg: SLCR offset and size taken via syscon <0x200 0x48>
10 - syscon: <&slcr>
12 - #reset-cells: Must be 1
14 The Zynq Reset Manager needs to be a childnode of the SLCR.
18 compatible = "xlnx,zynq-reset";
20 #reset-cells = <1>;
[all …]
/linux/arch/arm/mach-meson/
H A Dplatsmp.c1 // SPDX-License-Identifier: GPL-2.0-or-later
10 #include <linux/of.h>
13 #include <linux/reset.h>
23 #define MESON_SMP_SRAM_CPU_CTRL_ADDR_REG(c) (0x04 + ((c - 1) << 2))
31 #define MESON_CPU_PWR_A9_MEM_PD0_M(c) (0x0f << (32 - (c * 4)))
106 meson_smp_prepare_cpus("arm,cortex-a5-scu", "amlogic,meson8b-pmu", in meson8b_smp_prepare_cpus()
107 "amlogic,meson8b-smp-sram"); in meson8b_smp_prepare_cpus()
112 meson_smp_prepare_cpus("arm,cortex-a9-scu", "amlogic,meson8-pmu", in meson8_smp_prepare_cpus()
113 "amlogic,meson8-smp-sram"); in meson8_smp_prepare_cpus()
121 * system without power-cycling, or when taking the CPU offline and in meson_smp_begin_secondary_boot()
[all …]
/linux/Documentation/devicetree/bindings/sound/
H A Dimg,i2s-out.txt5 - compatible : Compatible list, must contain "img,i2s-out"
7 - #sound-dai-cells : Must be equal to 0
9 - reg : Offset and length of the register set for the device
11 - clocks : Contains an entry for each entry in clock-names
13 - clock-names : Must include the following entries:
17 - dmas: Contains an entry for each entry in dma-names.
19 - dma-names: Must include the following entry:
22 - img,i2s-channels : Number of I2S channels instantiated in the I2S out block
24 - resets: Contains a phandle to the I2S out reset signal
26 - reset-names: Contains the reset signal name "rst"
[all …]
H A Dimg,spdif-out.txt5 - compatible : Compatible list, must contain "img,spdif-out"
7 - #sound-dai-cells : Must be equal to 0
9 - reg : Offset and length of the register set for the device
11 - dmas: Contains an entry for each entry in dma-names.
13 - dma-names: Must include the following entry:
16 - clocks : Contains an entry for each entry in clock-names.
18 - clock-names : Includes the following entries:
22 - resets: Contains a phandle to the spdif out reset signal
24 - reset-names: Contains the reset signal name "rst"
28 - interrupts : Contains the parallel out interrupt, if present
[all …]
H A Dimg,parallel-out.txt5 - compatible : Compatible list, must contain "img,parallel-out".
7 - #sound-dai-cells : Must be equal to 0
9 - reg : Offset and length of the register set for the device.
11 - dmas: Contains an entry for each entry in dma-names.
13 - dma-names: Must include the following entry:
16 - clocks : Contains an entry for each entry in clock-names.
18 - clock-names : Includes the following entries:
22 - resets: Contains a phandle to the parallel out reset signal
24 - reset-names: Contains the reset signal name "rst"
28 - interrupts : Contains the parallel out interrupt, if present
[all …]
/linux/drivers/firewire/
H A Dcore-card.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2005-2007 Kristian Hoegsberg <krh@bitplanet.net>
8 #include <linux/crc-itu-t.h>
12 #include <linux/firewire-constants.h>
38 dev_name(card->device), &vaf); \
83 * IEEE-1394 specifies a default SPLIT_TIMEOUT value of 800 cycles (100 ms),
97 * Initialize contents of config rom buffer. On the OHCI in generate_config_rom()
101 * sure the contents of bus info block in host memory matches in generate_config_rom()
109 BIB_LINK_SPEED(card->link_speed) | in generate_config_rom()
110 BIB_GENERATION(card->config_rom_generation++ % 14 + 2) | in generate_config_rom()
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/linux/drivers/firmware/efi/
H A Dcapsule.c1 // SPDX-License-Identifier: GPL-2.0
25 static int efi_reset_type = -1;
34 * efi_capsule_pending - has a capsule been passed to the firmware?
35 * @reset_type: store the type of EFI reset if capsule is pending
38 * firmware we need to perform a specific type of reset. If a capsule is
39 * pending return the reset type in @reset_type.
41 * This function will race with callers of efi_capsule_update(), for
47 * A non-racy use is from platform reboot code because we use
63 * Whitelist of EFI capsule flags that we support.
74 * efi_capsule_supported - does the firmware support the capsule?
[all …]
/linux/drivers/usb/host/
H A Docteon-hcd.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * This file is subject to the terms and conditions of the GNU General Public
6 * License. See the file "COPYING" in the main directory of this archive
9 * Some parts of the code were originally released under BSD license:
11 * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights
18 * * Redistributions of source code must retain the above copyright
19 * notice, this list of conditions and the following disclaimer.
22 * copyright notice, this list of conditions and the following
26 * * Neither the name of Cavium Networks nor the names of
40 * OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
[all …]
/linux/drivers/gpu/drm/i915/gt/
H A Dintel_reset.c1 // SPDX-License-Identifier: MIT
3 * Copyright © 2008-2018 Intel Corporation
41 struct drm_i915_file_private *file_priv = ctx->file_priv; in client_mark_guilty()
52 prev_hang = xchg(&file_priv->hang_timestamp, jiffies); in client_mark_guilty()
57 atomic_add(score, &file_priv->ban_score); in client_mark_guilty()
59 drm_dbg(&ctx->i915->drm, in client_mark_guilty()
61 ctx->name, score, in client_mark_guilty()
62 atomic_read(&file_priv->ban_score)); in client_mark_guilty()
73 if (intel_context_is_closed(rq->context)) in mark_guilty()
77 ctx = rcu_dereference(rq->context->gem_context); in mark_guilty()
[all …]
/linux/arch/powerpc/platforms/52xx/
H A Dmpc52xx_common.c7 * This file is licensed under the terms of the GNU General Public License
8 * version 2. This program is licensed "as is" without any warranty of any
25 { .compatible = "fsl,mpc5200-xlb", },
26 { .compatible = "mpc5200-xlb", },
30 { .compatible = "fsl,mpc5200-immr", },
31 { .compatible = "fsl,mpc5200b-immr", },
32 { .compatible = "simple-bus", },
71 out_be32(&xlb->master_pri_enable, 0xff); in mpc5200_setup_xlb_arbiter()
72 out_be32(&xlb->master_priority, 0x11111111); in mpc5200_setup_xlb_arbiter()
77 * transaction and re-enable it afterwards ...) in mpc5200_setup_xlb_arbiter()
[all …]
/linux/drivers/gpu/drm/amd/display/modules/hdcp/
H A Dhdcp.c4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
8 * and/or sell copies of the Software, and to permit persons to whom the
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
31 struct mod_hdcp_trace *trace = &hdcp->connection.trace; in push_error_status()
33 if (trace->error_count < MAX_NUM_OF_ERROR_TRACE) { in push_error_status()
[all …]
/linux/drivers/misc/cxl/
H A Dhcalls.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
23 * This is straight out of PAPR, but replacing some of the compound fields with
26 * The 'flags' parameter regroups the various bit-fields
59 * cxl_h_detach_process - Detach a process element from a coherent
65 * cxl_h_reset_afu - Perform a reset to the coherent platform function.
70 * cxl_h_suspend_process - Suspend a process from being executed
71 * Parameter1 = process-token as returned from H_ATTACH_CA_PROCESS when
77 * cxl_h_resume_process - Resume a process to be executed
78 * Parameter1 = process-token as returned from H_ATTACH_CA_PROCESS when
84 * cxl_h_read_error_state - Reads the error state of the coherent
[all …]
H A Dhcalls.c1 // SPDX-License-Identifier: GPL-2.0-or-later
26 #define H_CONTROL_CA_FUNCTION_RESET 1 /* perform a reset */
35 #define H_CONTROL_CA_FUNCTION_GET_FUNCTION_ERR_INT 11 /* read the function-wide error data based …
36 #define H_CONTROL_CA_FUNCTION_ACK_FUNCTION_ERR_INT 12 /* acknowledge function-wide error data bas…
37 #define H_CONTROL_CA_FUNCTION_GET_ERROR_LOG 13 /* retrieve the Platform Log ID (PLID) of a…
42 #define H_CONTROL_CA_FACILITY_RESET 1 /* perform a reset */
90 "RESET", /* 1 */
107 "RESET", /* 1 */
157 return -EINVAL; in cxl_h_attach_process()
163 return -EBUSY; in cxl_h_attach_process()
[all …]
/linux/drivers/scsi/cxlflash/
H A Dmain.c1 // SPDX-License-Identifier: GPL-2.0-or-later
41 * process_cmd_err() - command error handler
49 struct afu *afu = cmd->parent; in process_cmd_err()
50 struct cxlflash_cfg *cfg = afu->parent; in process_cmd_err()
51 struct device *dev = &cfg->dev->dev; in process_cmd_err()
55 ioasa = &(cmd->sa); in process_cmd_err()
57 if (ioasa->rc.flags & SISL_RC_FLAGS_UNDERRUN) { in process_cmd_err()
58 resid = ioasa->resid; in process_cmd_err()
64 if (ioasa->rc.flags & SISL_RC_FLAGS_OVERRUN) { in process_cmd_err()
67 scp->result = (DID_ERROR << 16); in process_cmd_err()
[all …]
/linux/arch/powerpc/kernel/
H A Deeh.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Copyright 2001-2012 IBM Corporation.
23 #include <linux/of.h>
32 #include <asm/ppc-pci.h>
34 #include <asm/pte-walk.h>
40 * usual PCI framework, except by check-stopping the CPU. Systems
41 * that are designed for high-availability/reliability cannot afford
43 * An EEH-capable bridge operates by converting a detected error
44 * into a "slot freeze", taking the PCI adapter off-line, making
45 * the slot behave, from the OS'es point of view, as if the slot
[all …]
/linux/Documentation/driver-api/
H A Dreset.rst1 .. SPDX-License-Identifier: GPL-2.0-only
4 Reset controller API
10 Reset controllers are central units that control the reset signals to multiple
12 The reset controller API is split into two parts:
13 the `consumer driver interface <#consumer-driver-interface>`__ (`API reference
14 <#reset-consumer-api>`__), which allows peripheral drivers to request control
15 over their reset input signals, and the `reset controller driver interface
16 <#reset-controller-driver-interface>`__ (`API reference
17 <#reset-controller-driver-api>`__), which is used by drivers for reset
18 controller devices to register their reset controls to provide them to the
[all …]
/linux/drivers/net/ethernet/intel/igc/
H A Digc_phy.c1 // SPDX-License-Identifier: GPL-2.0
8 * igc_check_reset_block - Check if PHY reset is blocked
11 * Read the PHY management control register and check whether a PHY reset
12 * is blocked. If a reset is not blocked return 0, otherwise
26 * igc_get_phy_id - Retrieve the PHY ID and revision
34 struct igc_phy_info *phy = &hw->phy; in igc_get_phy_id()
38 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id); in igc_get_phy_id()
40 goto out; in igc_get_phy_id()
42 phy->id = (u32)(phy_id << 16); in igc_get_phy_id()
44 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id); in igc_get_phy_id()
[all …]
/linux/arch/arm/mach-bcm/
H A Dbcm63xx_pmb.c1 // SPDX-License-Identifier: GPL-2.0-or-later
11 #include <linux/reset/bcm63xx_pmb.h>
12 #include <linux/of.h>
97 return -ENODEV; in bcm63xx_pmb_get_resources()
100 ret = of_parse_phandle_with_args(dn, "resets", "#reset-cells", in bcm63xx_pmb_get_resources()
108 pr_err("reset-controller does not conform to reset-cells\n"); in bcm63xx_pmb_get_resources()
109 return -EINVAL; in bcm63xx_pmb_get_resources()
115 return -ENOMEM; in bcm63xx_pmb_get_resources()
118 /* We do not need the number of zones */ in bcm63xx_pmb_get_resources()
142 * value since we will use it later for CPU de-assert once done with in bcm63xx_pmb_power_on_cpu()
[all …]
/linux/drivers/scsi/csiostor/
H A Dcsio_hw.c2 * This file is part of the Chelsio FCoE driver for Linux.
4 * Copyright (c) 2008-2012 Chelsio Communications, Inc. All rights reserved.
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
9 * COPYING in the main directory of this source tree, or the
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
[all …]
/linux/drivers/scsi/arm/
H A Dfas216.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 1997-2000 Russell King
66 #define STAT_DATAOUT (0) /* Data out */
68 #define STAT_COMMAND (STAT_CD) /* Command out */
70 #define STAT_MESGOUT (STAT_MSG|STAT_CD) /* Message out */
86 #define INST_BUSRESET (1 << 7) /* SCSI Bus reset */
118 #define CNTL1_DISR (1 << 6) /* Disable Irq on SCSI reset */
123 #define CLKF_F37MHZ 0x00 /* 35.01 - 40 MHz */
125 #define CLKF_F12MHZ 0x03 /* 10.01 - 15 MHz */
126 #define CLKF_F17MHZ 0x04 /* 15.01 - 20 MHz */
[all …]
/linux/arch/arm/mach-omap2/
H A Dprminst44xx.c1 // SPDX-License-Identifier: GPL-2.0-only
18 #include "prcm-common.h"
23 #include "prm-regbits-44xx.h"
34 * omap_prm_base_init - Populates the prm partitions
36 * Populates the base addresses of the _prm_bases
37 * array used for read/write of prm module registers.
75 /* Read-modify-write a register in PRM. Caller must lock */
90 * omap4_prminst_is_hardreset_asserted - read the HW reset line state of
93 * @shift: register bit shift corresponding to the reset line to check
97 * -EINVAL upon parameter error.
[all …]
/linux/drivers/net/ethernet/intel/igb/
H A De1000_phy.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2007 - 2018 Intel Corporation. */
31 * igb_check_reset_block - Check if PHY reset is blocked
34 * Read the PHY management control register and check whether a PHY reset
35 * is blocked. If a reset is not blocked return 0, otherwise
48 * igb_get_phy_id - Retrieve the PHY ID and revision
56 struct e1000_phy_info *phy = &hw->phy; in igb_get_phy_id()
61 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211)) in igb_get_phy_id()
62 phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0); in igb_get_phy_id()
64 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id); in igb_get_phy_id()
[all …]
/linux/drivers/net/ethernet/intel/igbvf/
H A Dvf.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2009 - 2018 Intel Corporation. */
22 * e1000_init_mac_params_vf - Inits MAC params
27 struct e1000_mac_info *mac = &hw->mac; in e1000_init_mac_params_vf()
29 /* VF's have no MTA Registers - PF feature only */ in e1000_init_mac_params_vf()
30 mac->mta_reg_count = 128; in e1000_init_mac_params_vf()
32 mac->rar_entry_count = 1; in e1000_init_mac_params_vf()
35 /* reset */ in e1000_init_mac_params_vf()
36 mac->ops.reset_hw = e1000_reset_hw_vf; in e1000_init_mac_params_vf()
38 mac->ops.init_hw = e1000_init_hw_vf; in e1000_init_mac_params_vf()
[all …]
/linux/drivers/reset/
H A Dreset-ti-sci.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Texas Instrument's System Control Interface (TI-SCI) reset driver
5 * Copyright (C) 2015-2017 Texas Instruments Incorporated - https://www.ti.com/
12 #include <linux/of.h>
14 #include <linux/reset-controller.h>
18 * struct ti_sci_reset_control - reset control structure
19 * @dev_id: SoC-specific device identifier
20 * @reset_mask: reset mask to use for toggling reset
21 * @lock: synchronize reset_mask read-modify-writes
30 * struct ti_sci_reset_data - reset controller information structure
[all …]

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