Lines Matching +full:out +full:- +full:of +full:- +full:reset
1 /* SPDX-License-Identifier: GPL-2.0 */
5 * This file is subject to the terms and conditions of the GNU General Public
6 * License. See the file "COPYING" in the main directory of this archive
9 * Some parts of the code were originally released under BSD license:
11 * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights
18 * * Redistributions of source code must retain the above copyright
19 * notice, this list of conditions and the following disclaimer.
22 * copyright notice, this list of conditions and the following
26 * * Neither the name of Cavium Networks nor the names of
40 * OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
41 * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
42 * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
44 * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR
45 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
104 * This register can be used to configure the core after power-on or a change in
105 * mode of operation. This register mainly contains AHB system-related
110 * The application must program this register as part of the O2P USB core
126 * @nptxfemplvl: Non-Periodic TxFIFO Empty Level (NPTxFEmpLvl)
128 * Indicates when the Non-Periodic TxFIFO Empty Interrupt bit in
131 * * 1'b0: GINTSTS.NPTxFEmp interrupt indicates that the Non-
133 * * 1'b1: GINTSTS.NPTxFEmp interrupt indicates that the Non-
143 * line assertion to itself. Irrespective of this bit's setting,
165 * This register contains the configuration options of the O2P USB core.
172 * This value is in terms of 32-bit words.
181 * @rsttype: Reset Style for Clocked always Blocks in RTL (RstType)
182 * * 1'b0: Asynchronous reset is used in the core
183 * * 1'b1: Synchronous reset is used in the core
199 * @pktsizewidth: Width of Packet Size Counters (PktSizeWidth)
208 * @xfersizewidth: Width of Transfer Size Counters (XferSizeWidth)
211 * - ...
256 * Incomplete Isochronous OUT Transfer Mask
260 * @oepintmsk: OUT Endpoints Interrupt Mask (OEPIntMsk)
263 * @eopfmsk: End of Periodic Frame Interrupt Mask (EOPFMsk)
264 * @isooutdropmsk: Isochronous OUT Packet Dropped Interrupt Mask
267 * @usbrstmsk: USB Reset Mask (USBRstMsk)
273 * @goutnakeffmsk: Global OUT NAK Effective Mask (GOUTNakEffMsk)
274 * @ginnakeffmsk: Global Non-Periodic IN NAK Effective Mask
276 * @nptxfempmsk: Non-Periodic TxFIFO Empty Mask (NPTxFEmpMsk)
277 * @rxflvlmsk: Receive FIFO Non-Empty Mask (RxFLvlMsk)
278 * @sofmsk: Start of (micro)Frame Mask (SofMsk)
324 * This register interrupts the application for system-level events in the
325 * current mode of operation (Device mode or Host mode). It is shown in
326 * Interrupt. Some of the bits in this register are valid only in Host mode,
328 * current mode of operation. In order to clear the interrupt status bits of
343 * Power-Down and Clock Gating Programming Model" on
351 * Power-Down and Clock Gating Programming Model" on
367 * on one of the channels of the core (in Host mode). The
369 * register to determine the exact number of the channel on which
371 * Channel-n Interrupt (HCINTn) register to determine the exact
372 * cause of the interrupt. The application must clear the
375 * The core sets this bit to indicate a change in port status of
376 * one of the O2P USB core ports in Host mode. The application must
384 * endpoints due to the unavailability of TxFIFO space or Request
391 * Incomplete Isochronous OUT Transfer (incompISOOUT)
393 * there is at least one isochronous OUT endpoint on which the
395 * interrupt is asserted along with the End of Periodic Frame
401 * along with the End of Periodic Frame Interrupt (EOPF) bit in
403 * @oepint: OUT Endpoints Interrupt (OEPInt)
405 * on one of the OUT endpoints of the core (in Device mode). The
407 * (DAINT) register to determine the exact number of the OUT
409 * corresponding Device OUT Endpoint-n Interrupt (DOEPINTn)
410 * register to determine the exact cause of the interrupt. The
415 * on one of the IN endpoints of the core (in Device mode). The
417 * (DAINT) register to determine the exact number of the IN
419 * corresponding Device IN Endpoint-n Interrupt (DIEPINTn)
420 * register to determine the exact cause of the interrupt. The
424 * Indicates that an IN token has been received for a non-periodic
426 * top of the Non-Periodic Transmit FIFO and the IN endpoint
428 * @eopf: End of Periodic Frame Interrupt (EOPF)
430 * Interval field of the Device Configuration register
432 * @isooutdrop: Isochronous OUT Packet Dropped Interrupt (ISOOutDrop)
433 * The core sets this bit when it fails to write an isochronous OUT
436 * for the isochronous OUT endpoint.
441 * @usbrst: USB Reset (USBRst)
442 * The core sets this bit to indicate that a reset is detected on
448 * period of time.
456 * @goutnakeff: Global OUT NAK Effective (GOUTNakEff)
457 * Indicates that the Set Global OUT NAK bit in the Device Control
460 * Global OUT NAK bit in the Device Control register
462 * @ginnakeff: Global IN Non-Periodic NAK Effective (GINNakEff)
463 * Indicates that the Set Global Non-Periodic IN NAK bit in the
467 * can be cleared by clearing the Clear Global Non-Periodic IN
470 * is sent out on the USB. The STALL bit takes precedence over
472 * @nptxfemp: Non-Periodic TxFIFO Empty (NPTxFEmp)
473 * This interrupt is asserted when the Non-Periodic TxFIFO is
475 * one entry to be written to the Non-Periodic Transmit Request
477 * the Non-Periodic TxFIFO Empty Level bit in the Core AHB
479 * @rxflvl: RxFIFO Non-Empty (RxFLvl)
482 * @sof: Start of (micro)Frame (Sof)
484 * (FS), micro-SOF (HS), or Keep-Alive (LS) is transmitted on the
506 * affect the operation of the core.
507 * @curmod: Current Mode of Operation (CurMod)
508 * Indicates the current mode of operation.
552 * Non-Periodic Transmit FIFO Size Register (GNPTXFSIZ)
555 * Non-Periodic TxFIFO.
561 * @nptxfdep: Non-Periodic TxFIFO Depth (NPTxFDep)
562 * This value is in terms of 32-bit words.
565 * @nptxfstaddr: Non-Periodic Transmit RAM Start Address (NPTxFStAddr)
566 * This field contains the memory start address for Non-Periodic
579 * Non-Periodic Transmit FIFO/Queue Status Register (GNPTXSTS)
581 * This read-only register contains the free space information for the
582 * Non-Periodic TxFIFO and the Non-Periodic Transmit Request Queue.
588 * @nptxqtop: Top of the Non-Periodic Transmit Request Queue (NPTxQTop)
589 * Entry in the Non-Periodic Tx Request Queue that is currently
593 * - 2'b00: IN/OUT token
594 * - 2'b01: Zero-length transmit packet (device IN/host OUT)
595 * - 2'b10: PING/CSPLIT token
596 * - 2'b11: Channel halt command
598 * @nptxqspcavail: Non-Periodic Transmit Request Queue Space Available
600 * Indicates the amount of free space available in the Non-
602 * and OUT requests in Host mode. Device mode has only IN
604 * * 8'h0: Non-Periodic Transmit Request Queue is full
609 * @nptxfspcavail: Non-Periodic TxFIFO Space Avail (NPTxFSpcAvail)
610 * Indicates the amount of free space available in the Non-
612 * Values are in terms of 32-bit words.
613 * * 16'h0: Non-Periodic TxFIFO is full
632 * Core Reset Register (GRSTCTL)
634 * The application uses this register to reset various hardware features inside
650 * * 5'h0: Non-Periodic TxFIFO flush
654 * - ...
656 * * 5'h10: Flush all the Periodic and Non-Periodic TxFIFOs in the
660 * cannot do so if the core is in the midst of a transaction.
665 * performing any operations. This bit takes 8 clocks (of phy_clk
669 * must first ensure that the core is not in the middle of a
676 * (slowest of PHY or AHB clock) to clear.
680 * @frmcntrrst: Host Frame Counter Reset (FrmCntrRst)
681 * The application writes this bit to reset the (micro)frame number
682 * counter inside the core. When the (micro)frame counter is reset,
683 * the subsequent SOF sent out by the core will have a
684 * (micro)frame number of 0.
685 * @hsftrst: HClk Soft Reset (HSftRst)
687 * AHB Clock domain. Only AHB Clock Domain pipelines are reset.
689 * * All state machines in the AHB clock domain are reset to the
698 * can get the status of any core events that occurred after it set
700 * This is a self-clearing bit that the core clears after all
701 * necessary logic is reset in the core. This may take several
703 * @csftrst: Core Soft Reset (CSftRst)
707 * - PCGCCTL.RstPdwnModule
708 * - PCGCCTL.GateHclk
709 * - PCGCCTL.PwrClmp
710 * - PCGCCTL.StopPPhyLPwrClkSelclk
711 * - GUSBCFG.PhyLPwrClkSel
712 * - GUSBCFG.DDRSel
713 * - GUSBCFG.PHYSel
714 * - GUSBCFG.FSIntf
715 * - GUSBCFG.ULPI_UTMI_Sel
716 * - GUSBCFG.PHYIf
717 * - HCFG.FSLSPclkSel
718 * - DCFG.DevSpd
720 * reset to the IDLE state, and all the transmit FIFOs and the
723 * as possible, after gracefully completing the last data phase of
726 * The application can write to this bit any time it wants to reset
727 * the core. This is a self-clearing bit and the core clears this
728 * bit after all the necessary logic is reset in the core, which
729 * may take several clocks, depending on the current state of the
733 * bit 31 of this register is 1 (AHB Master is IDLE) before
735 * Typically software reset is used during software development
740 * selected, the PHY domain has to be reset for proper operation.
770 * This value is in terms of 32-bit words.
787 * pops the top data entry out of the RxFIFO.
800 * Indicates the status of the received packet
812 * Indicates the byte count of the received IN data packet
832 * This register can be used to configure the core after power-on or a changing
833 * to Host mode or Device mode. It contains USB and USB-PHY related
844 * @phylpwrclksel: PHY Low-Power Clock Select (PhyLPwrClkSel)
846 * Selects either 480-MHz or 48-MHz (low-power) PHY mode. In
847 * FS and LS modes, the PHY can usually operate on a 48-MHz
849 * * 1'b0: 480-MHz Internal PLL clock
850 * * 1'b1: 48-MHz External Clock
852 * 30-MHz, depending upon whether 8- or 16-bit data width is
853 * selected. In 48-MHz mode, the UTMI interface operates at 48
863 * @hnpcap: HNP-Capable (HNPCap)
865 * @srpcap: SRP-Capable (SRPCap)
869 * @physel: USB 2.0 High-Speed PHY or USB 1.1 Full-Speed Serial
871 * @fsintf: Full-Speed Serial Interface Select (FSIntf)
878 * The number of PHY clocks that the application programs in this
879 * field is added to the high-speed/full-speed interpacket timeout
884 * The USB standard timeout value for high-speed operation is
886 * value for full-speed operation is 16 to 18 (inclusive) bit
888 * speed of enumeration. The number of bit times added per PHY
890 * High-speed operation:
891 * * One 30-MHz PHY clock = 16 bit times
892 * * One 60-MHz PHY clock = 8 bit times
893 * Full-speed operation:
894 * * One 30-MHz PHY clock = 0.4 bit times
895 * * One 60-MHz PHY clock = 0.2 bit times
896 * * One 48-MHz PHY clock = 0.25 bit times
922 * register interrupts the application using the Host Channels Interrupt bit of
924 * There is one interrupt bit per channel, up to a maximum of 16 bits. Bits in
926 * in the corresponding Host Channel-n Interrupt register.
949 * channel. There is one interrupt mask bit per channel, up to a maximum of 16
970 * Host Channel-n Characteristics Register (HCCHAR)
988 * This field is set (reset) by the application to indicate that
998 * When the Split Enable bit of the Host Channel-n Split Control
999 * register (HCSPLTn.SpltEna) is reset (1'b0), this field indicates
1000 * to the host the number of transactions that should be executed
1009 * number of immediate retries to be performed for a periodic split
1018 * @lspddev: Low-Speed Device (LSpdDev)
1020 * channel is communicating to a low-speed device.
1022 * Indicates whether the transaction is IN or OUT.
1023 * * 1'b0: OUT
1029 * Indicates the maximum packet size of the associated endpoint.
1052 * This register configures the core after power-on. Do not make changes to this
1059 * @fslssupp: FS- and LS-Only Support (FSLSSupp)
1067 * * 1'b1: FS/LS-only, even if the connected device can support HS
1084 * do a soft reset.
1098 * Host Channel-n Interrupt Register (HCINT)
1100 * This register indicates the status of a channel with respect to USB- and
1101 * AHB-related events. The application must read this register when the Host
1102 * Channels Interrupt bit of the Core Interrupt register (GINTSTS.HChInt) is
1105 * number for the Host Channel-n Interrupt register. The application must clear
1123 * Indicates the transfer completed abnormally either because of
1149 * Host Channel-n Interrupt Mask Register (HCINTMSKn)
1191 * Host Channel-n Split Control Register (HCSPLT)
1206 * middle, or last payloads with each OUT transaction.
1207 * * 2'b11: All. This is the entire data payload is of this
1209 * * 2'b10: Begin. This is the first data payload of this
1211 * * 2'b00: Mid. This is the middle payload of this transaction
1213 * * 2'b01: End. This is the last payload of this transaction
1216 * This field holds the device address of the transaction
1219 * This field is the port number of the recipient transaction
1236 * Host Channel-n Transfer Size Register (HCTSIZ)
1246 * The application programs this field with the type of PID to use
1248 * for the rest of the transfer.
1252 * * 2'b11: MDATA (non-control)/SETUP (control)
1255 * number of packets to be transmitted (OUT) or received (IN).
1257 * transmission or reception of an OUT/IN packet. Once this count
1261 * For an OUT, this field is the number of data bytes the host will
1265 * program this field as an integer multiple of the maximum packet
1266 * size for IN transactions (periodic and non-periodic).
1291 * the interval between two consecutive SOFs (FS) or micro-
1292 * SOFs (HS) or Keep-Alive tokens (HS). This field contains the
1293 * number of PHY clocks that constitute the required frame
1296 * write a value to this register only after the Port Enable bit of
1300 * Clock Select field of the Host Configuration register
1301 * (HCFG.FSLSPclkSel). Do not change the value of this field
1319 * It also indicates the time remaining (in terms of the number of PHY clocks)
1327 * Indicates the amount of time remaining in the current
1328 * microframe (HS) or frame (FS/LS), in terms of PHY clocks.
1334 * USB, and is reset to 0 when it reaches 16'h3FFF.
1350 * A single register holds USB port-related information such as USB reset,
1353 * through the Host Port Interrupt bit of the Core Interrupt register
1363 * Indicates the speed of the device attached to this port.
1379 * PrtSpd must be zero (i.e. the interface must be in high-speed
1388 * * Bit [10]: Logic level of D-
1389 * * Bit [11]: Logic level of D+
1390 * @prtrst: Port Reset (PrtRst)
1391 * When the application sets this bit, a reset sequence is
1392 * started on this port. The application must time the reset
1393 * period and clear this bit after the reset sequence is
1395 * * 1'b0: Port not in reset
1396 * * 1'b1: Port in reset
1398 * minimum duration mentioned below to start a reset on the
1409 * Clock Stop bit, which will assert the suspend input pin of
1411 * The read value of this bit reflects the current suspend
1412 * status of the port. This bit is cleared by the core after a
1414 * the Port Reset bit or Port Resume bit in this register or the
1427 * Interrupt bit of the Core Interrupt register
1430 * when it detects a disconnect condition. The read value of
1436 * The core sets this bit when the status of the Port
1439 * Indicates the overcurrent condition of the port.
1443 * The core sets this bit when the status of the Port Enable bit
1444 * [2] of this register changes.
1446 * A port is enabled only by the core after a reset sequence,
1457 * Interrupt bit of the Core Interrupt register (GINTSTS.PrtInt).
1489 * This register holds the size and the memory start address of the Periodic
1497 * This value is in terms of 32-bit words.
1514 * This read-only register contains the free space information for the Periodic
1521 * @ptxqtop: Top of the Periodic Transmit Request Queue (PTxQTop)
1526 * - 1'b0: send in even (micro)frame
1527 * - 1'b1: send in odd (micro)frame
1530 * - 2'b00: IN/OUT
1531 * - 2'b01: Zero-length packet
1532 * - 2'b10: CSPLIT
1533 * - 2'b11: Disable channel command
1538 * Indicates the number of free locations available to be written
1540 * IN and OUT requests.
1548 * Indicates the number of free locations available to be written
1550 * Values are in terms of 32-bit words
1571 * This register is used to control the frequency of the hclk and the
1582 * ratio of eclk/hclk is currently 16.
1585 * @hclk_rst: When this field is '0' the HCLK-DIVIDER used to
1587 * in reset. This bit must be set to '0' before
1589 * The reset to the HCLK_DIVIDERis also asserted
1590 * when core reset is asserted.
1591 * @p_x_on: Force USB-PHY on during suspend.
1592 * '1' USB-PHY XO block is powered-down during
1594 * '0' USB-PHY XO block is powered-up during
1596 * The value of this field must be set while POR is
1600 * '0' The USB-PHY uses a 12MHz crystal as a clock source
1615 * @p_com_on: '0' Force USB-PHY XO Bias, Bandgap and PLL to
1617 * '1' The USB-PHY XO Bias, Bandgap and PLL are
1619 * The value of this field must be set while POR is
1627 * The value of this field must be set while POR is
1636 * @por: Power On Reset for the PHY.
1638 * @enable: When '1' allows the generation of the hclk. When
1640 * field of this register.
1641 * @prst: When this field is '0' the reset associated with
1643 * help in reset. This bit should not be set to '1'
1648 * @hrst: When this field is '0' the reset associated with
1650 * held in reset.This bit should not be set to '1'
1654 * @divide: The frequency of 'hclk' used by the USB subsystem
1655 * is the eclk frequency divided by the value of
1657 * DIVIDE2 of this register.
1661 * The ENABLE field of this register should not be set
1698 * @txhsxvtune: Transmitter High-Speed Crossover Adjustment
1703 * @portreset: Per_Port Reset
1705 * @lsbist: Low-Speed BIST Enable.
1706 * @fsbist: Full-Speed BIST Enable.
1707 * @hsbist: High-Speed BIST Enable.
1709 * Asserted at the end of the PHY BIST sequence.
1713 * @tdata_out: PHY Test Data Out.
1715 * test register contents, based upon the value of
1717 * @siddq: Drives the USBP (USB-PHY) SIDDQ input.
1721 * - still provide 3.3V to USB_VDD33, and
1722 * - tie USB_REXT to 3.3V supply, and
1723 * - set USBN*_USBP_CTL_STATUS[SIDDQ]=1
1724 * @txpreemphasistune: HS Transmitter Pre-Emphasis Enable
1726 * with byte-counts between packets. When set to 0
1728 * 4-byte aligned address after adding byte-count.
1733 * @dp_pulld: PHY DP_PULLDOWN input to the USB-PHY.
1734 * This signal enables the pull-down resistance on
1735 * the D+ line. '1' pull down-resistance is connected
1738 * (downstream-facing port), dp_pulldown and
1741 * @dm_pulld: PHY DM_PULLDOWN input to the USB-PHY.
1742 * This signal enables the pull-down resistance on
1743 * the D- line. '1' pull down-resistance is connected
1744 * to D-. '0' pull down resistance is not connected
1745 * to D-. When an A/B device is acting as a host
1746 * (downstream-facing port), dp_pulldown and
1751 * set while the USB is in reset.
1752 * @tuning: Transmitter Tuning for High-Speed Operation.
1754 * times for high-speed operation.
1769 * when bit-stuffing is enabled.
1772 * when bit-stuffing is enabled.
1781 * input and output of applicable analog test signals.
1783 * @bist_enb: Built-In Self Test Enable.
1785 * @tdata_sel: Test Data Out Select.
1796 * @ate_reset: Reset input from automatic test equipment.
1800 * free_clk, then re-enable them with an aligned
1805 * de-assertion.