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/linux/arch/arm/boot/dts/samsung/
H A Dexynos5422-odroid-core.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Hardkernel Odroid XU3/XU3-Lite/XU4/HC1 boards core device tree source
6 * Copyright (c) 2013-2017 Samsung Electronics Co., Ltd.
10 #include <dt-bindings/clock/samsung,s2mps11.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/gpio/gpio.h>
14 #include "exynos5422-cpus.dtsi"
27 stdout-path = "serial2:115200n8";
31 compatible = "samsung,secure-firmware";
35 fixed-rate-clocks {
[all …]
H A Dexynos4212.dtsi1 // SPDX-License-Identifier: GPL-2.0
23 #address-cells = <1>;
24 #size-cells = <0>;
26 cpu-map {
39 compatible = "arm,cortex-a9";
42 clock-names = "cpu";
43 operating-points-v2 = <&cpu0_opp_table>;
44 #cooling-cells = <2>; /* min followed by max */
49 compatible = "arm,cortex-a9";
52 clock-names = "cpu";
[all …]
H A Dexynos4210.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
7 * Copyright (c) 2010-2011 Linaro Ltd.
20 #include "exynos4-cpu-thermal.dtsi"
31 bus_acp: bus-acp {
32 compatible = "samsung,exynos-bus";
34 clock-names = "bus";
35 operating-points-v2 = <&bus_acp_opp_table>;
38 bus_acp_opp_table: opp-table {
39 compatible = "operating-points-v2";
[all …]
H A Dexynos4412.dtsi1 // SPDX-License-Identifier: GPL-2.0
23 #address-cells = <1>;
24 #size-cells = <0>;
26 cpu-map {
45 compatible = "arm,cortex-a9";
48 clock-names = "cpu";
49 operating-points-v2 = <&cpu0_opp_table>;
50 #cooling-cells = <2>; /* min followed by max */
55 compatible = "arm,cortex-a9";
58 clock-names = "cpu";
[all …]
H A Dexynos4x12.dtsi1 // SPDX-License-Identifier: GPL-2.0
19 #include "exynos4-cpu-thermal.dtsi"
27 fimc-lite0 = &fimc_lite_0;
28 fimc-lite1 = &fimc_lite_1;
31 bus_acp: bus-acp {
32 compatible = "samsung,exynos-bus";
34 clock-names = "bus";
35 operating-points-v2 = <&bus_acp_opp_table>;
38 bus_acp_opp_table: opp-table {
39 compatible = "operating-points-v2";
[all …]
/linux/arch/arm64/boot/dts/amlogic/
H A Dmeson-g12b-odroid-go-ultra.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include "meson-g12b-s922x.dtsi"
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/leds/common.h>
11 #include <dt-bindings/gpio/meson-g12a-gpio.h>
12 #include <dt-bindings/sound/meson-g12a-toacodec.h>
13 #include <dt-bindings/sound/meson-g12a-tohdmitx.h>
16 compatible = "hardkernel,odroid-go-ultra", "amlogic,s922x", "amlogic,g12b";
17 model = "Hardkernel ODROID-GO-Ultra";
[all …]
/linux/arch/arm/boot/dts/nvidia/
H A Dtegra124-peripherals-opp.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 emc_icc_dvfs_opp_table: opp-table-emc {
5 compatible = "operating-points-v2";
7 opp-12750000-800 {
8 opp-microvolt = <800000 800000 1150000>;
9 opp-hz = /bits/ 64 <12750000>;
10 opp-supported-hw = <0x0003>;
13 opp-12750000-950 {
14 opp-microvolt = <950000 950000 1150000>;
15 opp-hz = /bits/ 64 <12750000>;
[all …]
H A Dtegra20-cpu-opp.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 cpu0_opp_table: opp-table-cpu0 {
5 compatible = "operating-points-v2";
6 opp-shared;
8 opp-216000000-750 {
9 clock-latency-ns = <400000>;
10 opp-supported-hw = <0x0F 0x0003>;
11 opp-hz = /bits/ 64 <216000000>;
12 opp-suspend;
15 opp-216000000-800 {
[all …]
H A Dtegra30-cpu-opp.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 cpu0_opp_table: opp-table-cpu0 {
5 compatible = "operating-points-v2";
6 opp-shared;
8 opp-51000000-800 {
9 clock-latency-ns = <100000>;
10 opp-supported-hw = <0x1F 0x31FE>;
11 opp-hz = /bits/ 64 <51000000>;
14 opp-51000000-850 {
15 clock-latency-ns = <100000>;
[all …]
/linux/arch/arm64/boot/dts/nvidia/
H A Dtegra132-peripherals-opp.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 /* EMC DVFS OPP table */
5 emc_icc_dvfs_opp_table: opp-table-dvfs0 {
6 compatible = "operating-points-v2";
8 opp-12750000-800 {
9 opp-microvolt = <800000 800000 1150000>;
10 opp-hz = /bits/ 64 <12750000>;
11 opp-supported-hw = <0x0003>;
14 opp-12750000-950 {
15 opp-microvolt = <950000 950000 1150000>;
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mm-phycore-som.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/net/ti-dp83867.h>
11 model = "PHYTEC phyCORE-i.MX8MM";
12 compatible = "phytec,imx8mm-phycore-som", "fsl,imx8mm";
24 reg_vdd_3v3_s: regulator-vdd-3v3-s {
25 compatible = "regulator-fixed";
26 regulator-always-on;
27 regulator-boot-on;
28 regulator-max-microvolt = <3300000>;
29 regulator-min-microvolt = <3300000>;
[all …]
H A Dimx8qm.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2018-2019 NXP
7 #include <dt-bindings/clock/imx8-lpcg.h>
8 #include <dt-bindings/firmware/imx/rsrc.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/pinctrl/pads-imx8qm.h>
12 #include <dt-bindings/thermal/thermal.h>
15 interrupt-parent = <&gic>;
16 #address-cells = <2>;
[all …]
/linux/Documentation/devicetree/bindings/opp/
H A Dopp-v2.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/opp/opp-v2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Generic OPP (Operating Performance Points)
10 - Viresh Kumar <viresh.kumar@linaro.org>
13 - $ref: opp-v2-base.yaml#
17 const: operating-points-v2
22 - |
24 * Example 1: Single cluster Dual-core ARM cortex A9, switch DVFS states
[all …]
H A Dopp-v2-base.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/opp/opp-v2-base.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Generic OPP (Operating Performance Points) Common Properties
10 - Viresh Kumar <viresh.kumar@linaro.org>
13 Devices work at voltage-current-frequency combinations and some implementations
25 pattern: '^opp-table(-[a-z0-9]+)?$'
27 opp-shared:
29 Indicates that device nodes using this OPP Table Node's phandle switch
[all …]
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx7d.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
7 #include <dt-bindings/reset/imx7-reset.h>
18 clock-frequency = <996000000>;
19 operating-points-v2 = <&cpu0_opp_table>;
20 #cooling-cells = <2>;
21 nvmem-cells = <&fuse_grade>;
22 nvmem-cell-names = "speed_grade";
26 compatible = "arm,cortex-a7";
29 clock-frequency = <996000000>;
30 operating-points-v2 = <&cpu0_opp_table>;
[all …]
/linux/drivers/clk/tegra/
H A Dclk-device.c1 // SPDX-License-Identifier: GPL-2.0-only
4 #include <linux/clk-provider.h>
33 struct device *dev = clk_dev->dev; in tegra_clock_set_pd_state()
34 struct dev_pm_opp *opp; in tegra_clock_set_pd_state() local
37 opp = dev_pm_opp_find_freq_ceil(dev, &rate); in tegra_clock_set_pd_state()
38 if (opp == ERR_PTR(-ERANGE)) { in tegra_clock_set_pd_state()
47 dev_dbg(dev, "failed to find ceil OPP for %luHz\n", rate); in tegra_clock_set_pd_state()
48 opp = dev_pm_opp_find_freq_floor(dev, &rate); in tegra_clock_set_pd_state()
51 if (IS_ERR(opp)) { in tegra_clock_set_pd_state()
52 dev_err(dev, "failed to find OPP for %luHz: %pe\n", rate, opp); in tegra_clock_set_pd_state()
[all …]
/linux/arch/arm/boot/dts/rockchip/
H A Drk3229.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
11 /delete-node/ opp-table0;
13 cpu0_opp_table: opp-table-0 {
14 compatible = "operating-points-v2";
15 opp-shared;
17 opp-408000000 {
18 opp-hz = /bits/ 64 <408000000>;
19 opp-microvolt = <950000>;
20 clock-latency-ns = <40000>;
21 opp-suspend;
[all …]
/linux/drivers/opp/
H A Ddebugfs.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Generic OPP debugfs interface
5 * Copyright (C) 2015-2016 Viresh Kumar <viresh.kumar@linaro.org>
18 #include "opp.h"
24 if (dev->parent) in opp_set_dev_name()
25 snprintf(name, NAME_MAX, "%s-%s", dev_name(dev->paren in opp_set_dev_name()
31 opp_debug_remove_one(struct dev_pm_opp * opp) opp_debug_remove_one() argument
56 opp_debug_create_bw(struct dev_pm_opp * opp,struct opp_table * opp_table,struct dentry * pdentry) opp_debug_create_bw() argument
79 opp_debug_create_clks(struct dev_pm_opp * opp,struct opp_table * opp_table,struct dentry * pdentry) opp_debug_create_clks() argument
97 opp_debug_create_supplies(struct dev_pm_opp * opp,struct opp_table * opp_table,struct dentry * pdentry) opp_debug_create_supplies() argument
129 opp_debug_create_one(struct dev_pm_opp * opp,struct opp_table * opp_table) opp_debug_create_one() argument
[all...]
/linux/drivers/gpu/drm/panthor/
H A Dpanthor_devfreq.c1 // SPDX-License-Identifier: GPL-2.0 or MIT
16 * struct panthor_devfreq - Device frequency management
52 last = pdevfreq->time_last_update; in panthor_devfreq_update_utilization()
54 if (pdevfreq->last_busy_state) in panthor_devfreq_update_utilization()
55 pdevfreq->busy_time += ktime_sub(now, last); in panthor_devfreq_update_utilization()
57 pdevfreq->idle_time += ktime_sub(now, last); in panthor_devfreq_update_utilization()
59 pdevfreq->time_last_update = now; in panthor_devfreq_update_utilization()
66 struct dev_pm_opp *opp; in panthor_devfreq_target() local
69 opp = devfreq_recommended_opp(dev, freq, flags); in panthor_devfreq_target()
70 if (IS_ERR(opp)) in panthor_devfreq_target()
[all …]
/linux/drivers/cpufreq/
H A Dcpufreq-dt.c1 // SPDX-License-Identifier: GPL-2.0-only
25 #include "cpufreq-dt.h"
41 NULL, /* Extra space for boost-attr if required */
50 if (cpumask_test_cpu(cpu, priv->cpus)) in cpufreq_dt_find_data()
59 struct private_data *priv = policy->driver_data; in set_target()
60 unsigned long freq = policy->freq_table[index].frequency; in set_target()
62 return dev_pm_opp_set_rate(priv->cpu_dev, freq * 1000); in set_target()
66 * An earlier version of opp-v1 bindings used to name the regulator
67 * "cpu0-supply", we still need to handle that for backwards compatibility.
71 struct device_node *np __free(device_node) = of_node_get(dev->of_node); in find_supply_name()
[all …]
/linux/arch/arm/boot/dts/ti/omap/
H A Dam33xx.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/bus/ti-sysc.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/pinctrl/am33xx.h>
11 #include <dt-bindings/clock/am3.h>
15 interrupt-parent = <&intc>;
16 #address-cells = <1>;
17 #size-cells = <1>;
30 d-can0 = &dcan0;
[all …]
H A Domap34xx.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/bus/ti-sysc.h>
9 #include <dt-bindings/media/omap3-isp.h>
16 /* OMAP343x/OMAP35xx variants OPP1-6 */
17 operating-points-v2 = <&cpu0_opp_table>;
19 clock-latency = <300000>; /* From legacy driver */
20 #cooling-cells = <2>;
24 cpu0_opp_table: opp-table {
25 compatible = "operating-points-v2-ti-cpu";
[all …]
/linux/arch/arm64/boot/dts/rockchip/
H A Drk3588j.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include "rk3588-extra.dtsi"
10 cluster0_opp_table: opp-table-cluster0 {
11 compatible = "operating-points-v2";
12 opp-shared;
14 opp-1416000000 {
15 opp-hz = /bits/ 64 <1416000000>;
16 opp-microvolt = <750000 750000 950000>;
17 clock-latency-ns = <40000>;
18 opp-suspend;
[all …]
H A Drk3588-opp.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 cluster0_opp_table: opp-table-cluster0 {
5 compatible = "operating-points-v2";
6 opp-shared;
8 opp-1008000000 {
9 opp-hz = /bits/ 64 <1008000000>;
10 opp-microvolt = <675000 675000 950000>;
11 clock-latency-ns = <40000>;
13 opp-1200000000 {
14 opp-hz = /bits/ 64 <1200000000>;
[all …]
/linux/arch/arm64/boot/dts/ti/
H A Dk3-am625.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
7 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
10 /dts-v1/;
12 #include "k3-am62.dtsi"
16 #address-cells = <1>;
17 #size-cells = <0>;
19 cpu-map {
40 compatible = "arm,cortex-a53";
43 enable-method = "psci";
44 i-cache-size = <0x8000>;
[all …]

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