Searched +full:opp +full:- +full:fuse +full:- +full:level (Results 1 – 15 of 15) sorted by relevance
/linux/Documentation/devicetree/bindings/opp/ |
H A D | opp-v2-qcom-level.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/opp/opp-v2-qcom-level.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Qualcomm OPP 10 - Niklas Cassel <nks@flawful.org> 13 - $ref: opp-v2-base.yaml# 17 const: operating-points-v2-qcom-level 20 '^opp-?[0-9]+$': 25 opp-level: true [all …]
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/linux/Documentation/devicetree/bindings/power/avs/ |
H A D | qcom,cpr.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Niklas Cassel <nks@flawful.org> 14 or other device. Each OPP of a device corresponds to a "corner" that has 23 - enum: 24 - qcom,qcs404-cpr 25 - const: qcom,cpr 36 - description: Reference clock. 38 clock-names: [all …]
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/linux/Documentation/devicetree/bindings/cpufreq/ |
H A D | qcom-cpufreq-nvmem.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/cpufreq/qcom-cpufreq-nvmem.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Ilia Lin <ilia.lin@kernel.org> 17 on the CPU OPP in use. The CPUFreq driver sets the CPR power domain level 18 according to the required OPPs defined in the CPU OPP tables. 20 For old implementation efuses are parsed to select the correct opp table and 28 - qcom,apq8064 29 - qcom,apq8096 [all …]
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/linux/arch/arm64/boot/dts/freescale/ |
H A D | imx8mn.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 6 #include <dt-bindings/clock/imx8mn-clock.h> 7 #include <dt-bindings/power/imx8mn-power.h> 8 #include <dt-bindings/reset/imx8mq-reset.h> 9 #include <dt-bindings/gpio/gpio.h> 10 #include <dt-bindings/input/input.h> 11 #include <dt-bindings/interrupt-controller/arm-gic.h> 12 #include <dt-bindings/thermal/thermal.h> 14 #include "imx8mn-pinfunc.h" 17 interrupt-parent = <&gic>; [all …]
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H A D | imx8mm.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 6 #include <dt-bindings/clock/imx8mm-clock.h> 7 #include <dt-bindings/gpio/gpio.h> 8 #include <dt-bindings/input/input.h> 9 #include <dt-bindings/interrupt-controller/arm-gic.h> 10 #include <dt-bindings/power/imx8mm-power.h> 11 #include <dt-bindings/reset/imx8mq-reset.h> 12 #include <dt-bindings/thermal/thermal.h> 14 #include "imx8mm-pinfunc.h" 17 interrupt-parent = <&gic>; [all …]
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H A D | imx8mq.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 4 * Copyright (C) 2017-2018 Pengutronix, Lucas Stach <kernel@pengutronix.de> 7 #include <dt-bindings/clock/imx8mq-clock.h> 8 #include <dt-bindings/power/imx8mq-power.h> 9 #include <dt-bindings/reset/imx8mq-reset.h> 10 #include <dt-bindings/gpio/gpio.h> 11 #include "dt-bindings/input/input.h" 12 #include <dt-bindings/interrupt-controller/arm-gic.h> 13 #include <dt-bindings/thermal/thermal.h> 14 #include <dt-bindings/interconnect/imx8mq.h> [all …]
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/linux/drivers/memory/tegra/ |
H A D | tegra20-emc.c | 1 // SPDX-License-Identifier: GPL-2.0 14 #include <linux/interconnect-provider.h> 29 #include <soc/tegra/fuse.h> 221 /* protect shared rate-change code path */ 241 status = readl_relaxed(emc->regs + EMC_INTSTATUS) & intmask; in tegra_emc_isr() 247 dev_err_ratelimited(emc->dev, in tegra_emc_isr() 251 writel_relaxed(status, emc->regs + EMC_INTSTATUS); in tegra_emc_isr() 262 for (i = 0; i < emc->num_timing in tegra_emc_find_timing() 1112 struct dev_pm_opp *opp; tegra_emc_devfreq_target() local [all...] |
H A D | tegra124-emc.c | 1 // SPDX-License-Identifier: GPL-2.0-only 9 #include <linux/clk-provider.h> 15 #include <linux/interconnect-provider.h> 26 #include <soc/tegra/fuse.h> 512 /* protect shared rate-change code path */ 521 writel(value, emc->regs + EMC_CCFIFO_DATA); in emc_ccfifo_writel() 522 writel(offset, emc->reg in emc_ccfifo_writel() [all...] |
H A D | tegra30-emc.c | 1 // SPDX-License-Identifier: GPL-2.0+ 5 * Based on downstream driver from NVIDIA and tegra124-emc.c 6 * Copyright (C) 2011-2014 NVIDIA Corporation 9 * Copyright (C) 2019 GRATE-DRIVER project 18 #include <linux/interconnect-provider.h> 33 #include <soc/tegra/fuse.h> 392 /* protect shared rate-change code path */ 403 writel_relaxed(EMC_TIMING_UPDATE, emc->reg in emc_seq_update_timing() [all...] |
/linux/arch/arm/boot/dts/nvidia/ |
H A D | tegra30-cardhu.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 2 #include <dt-bindings/input/input.h> 3 #include <dt-bindings/thermal/thermal.h> 5 #include "tegra30-cpu-opp.dtsi" 6 #include "tegra30-cpu-opp-microvolt.dtsi" 16 * use tegra30-cardhu-a02.dts, Cardhu fab version A04 and later, use 17 * tegra30-cardhu-a04.dts. 20 * The sticker will have number like 600-81291-1000-002 C.3. In this 4th 22 * The (downstream internal) U-Boot of Cardhu display the board-id as 43 stdout-path = "serial0:115200n8"; [all …]
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H A D | tegra30.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 2 #include <dt-bindings/clock/tegra30-car.h> 3 #include <dt-bindings/gpio/tegra-gpio.h> 4 #include <dt-bindings/memory/tegra30-mc.h> 5 #include <dt-bindings/pinctrl/pinctrl-tegra.h> 6 #include <dt-bindings/interrupt-controller/arm-gic.h> 7 #include <dt-bindings/soc/tegra-pmc.h> 8 #include <dt-bindings/thermal/thermal.h> 10 #include "tegra30-peripherals-opp.dtsi" 14 interrupt-parent = <&lic>; [all …]
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H A D | tegra124.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 2 #include <dt-bindings/clock/tegra124-car.h> 3 #include <dt-bindings/gpio/tegra-gpio.h> 4 #include <dt-bindings/memory/tegra124-mc.h> 5 #include <dt-bindings/pinctrl/pinctrl-tegra.h> 6 #include <dt-bindings/interrupt-controller/arm-gic.h> 7 #include <dt-bindings/reset/tegra124-car.h> 8 #include <dt-bindings/thermal/tegra124-soctherm.h> 9 #include <dt-bindings/soc/tegra-pmc.h> 11 #include "tegra124-peripherals-opp.dtsi" [all …]
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H A D | tegra20.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 2 #include <dt-bindings/clock/tegra20-car.h> 3 #include <dt-bindings/gpio/tegra-gpio.h> 4 #include <dt-bindings/memory/tegra20-mc.h> 5 #include <dt-bindings/pinctrl/pinctrl-tegra.h> 6 #include <dt-bindings/interrupt-controller/arm-gic.h> 7 #include <dt-bindings/soc/tegra-pmc.h> 9 #include "tegra20-peripherals-opp.dtsi" 13 interrupt-parent = <&lic>; 14 #address-cells = <1>; [all …]
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/linux/arch/arm64/boot/dts/nvidia/ |
H A D | tegra132.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 2 #include <dt-bindings/clock/tegra124-car.h> 3 #include <dt-bindings/gpio/tegra-gpio.h> 4 #include <dt-bindings/memory/tegra124-mc.h> 5 #include <dt-bindings/pinctrl/pinctrl-tegra.h> 6 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h> 7 #include <dt-bindings/interrupt-controller/arm-gic.h> 8 #include <dt-bindings/thermal/tegra124-soctherm.h> 9 #include <dt-bindings/soc/tegra-pmc.h> 11 #include "tegra132-peripherals-opp.dtsi" [all …]
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/linux/ |
H A D | MAINTAINERS | 5 --------------------------------------------------- 21 W: *Web-page* with status/info 23 B: URI for where to file *bugs*. A web-page with detailed bug 28 patches to the given subsystem. This is either an in-tree file, 29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst 37 F: */net/* all files in "any top level directory"/net 46 N: [^a-z]tegra all files whose path contains tegra 64 ---------------- 83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS) 85 L: linux-scsi@vger.kernel.org [all …]
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