Lines Matching +full:opp +full:- +full:fuse +full:- +full:level

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   - Niklas Cassel <nks@flawful.org>
14   or other device. Each OPP of a device corresponds to a "corner" that has
23       - enum:
24           - qcom,qcs404-cpr
25       - const: qcom,cpr
36       - description: Reference clock.
38   clock-names:
40       - const: ref
42   vdd-apc-supply:
45   '#power-domain-cells':
48   operating-points-v2:
50       A phandle to the OPP table containing the performance states
53   acc-syscon:
57   nvmem-cells:
59       - description: Corner 1 quotient offset
60       - description: Corner 2 quotient offset
61       - description: Corner 3 quotient offset
62       - description: Corner 1 initial voltage
63       - description: Corner 2 initial voltage
64       - description: Corner 3 initial voltage
65       - description: Corner 1 quotient
66       - description: Corner 2 quotient
67       - description: Corner 3 quotient
68       - description: Corner 1 ring oscillator
69       - description: Corner 2 ring oscillator
70       - description: Corner 3 ring oscillator
71       - description: Fuse revision
73   nvmem-cell-names:
75       - const: cpr_quotient_offset1
76       - const: cpr_quotient_offset2
77       - const: cpr_quotient_offset3
78       - const: cpr_init_voltage1
79       - const: cpr_init_voltage2
80       - const: cpr_init_voltage3
81       - const: cpr_quotient1
82       - const: cpr_quotient2
83       - const: cpr_quotient3
84       - const: cpr_ring_osc1
85       - const: cpr_ring_osc2
86       - const: cpr_ring_osc3
87       - const: cpr_fuse_revision
90   - compatible
91   - reg
92   - interrupts
93   - clocks
94   - clock-names
95   - vdd-apc-supply
96   - '#power-domain-cells'
97   - operating-points-v2
98   - nvmem-cells
99   - nvmem-cell-names
104   - |
105     #include <dt-bindings/interrupt-controller/arm-gic.h>
107     cpr_opp_table: opp-table-cpr {
108         compatible = "operating-points-v2-qcom-level";
111             opp-level = <1>;
112             qcom,opp-fuse-level = <1>;
115             opp-level = <2>;
116             qcom,opp-fuse-level = <2>;
119             opp-level = <3>;
120             qcom,opp-fuse-level = <3>;
124     power-controller@b018000 {
125         compatible = "qcom,qcs404-cpr", "qcom,cpr";
129         clock-names = "ref";
130         vdd-apc-supply = <&pms405_s3>;
131         #power-domain-cells = <0>;
132         operating-points-v2 = <&cpr_opp_table>;
133         acc-syscon = <&tcsr>;
135         nvmem-cells = <&cpr_efuse_quot_offset1>,
148         nvmem-cell-names = "cpr_quotient_offset1",