Lines Matching +full:opp +full:- +full:fuse +full:- +full:level
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/imx8mn-clock.h>
7 #include <dt-bindings/power/imx8mn-power.h>
8 #include <dt-bindings/reset/imx8mq-reset.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/thermal/thermal.h>
14 #include "imx8mn-pinfunc.h"
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
19 #size-cells = <2>;
45 #address-cells = <1>;
46 #size-cells = <0>;
48 idle-states {
49 entry-method = "psci";
51 cpu_pd_wait: cpu-pd-wait {
52 compatible = "arm,idle-state";
53 arm,psci-suspend-param = <0x0010033>;
54 local-timer-stop;
55 entry-latency-us = <1000>;
56 exit-latency-us = <700>;
57 min-residency-us = <2700>;
63 compatible = "arm,cortex-a53";
65 clock-latency = <61036>;
67 enable-method = "psci";
68 i-cache-size = <0x8000>;
69 i-cache-line-size = <64>;
70 i-cache-sets = <256>;
71 d-cache-size = <0x8000>;
72 d-cache-line-size = <64>;
73 d-cache-sets = <128>;
74 next-level-cache = <&A53_L2>;
75 operating-points-v2 = <&a53_opp_table>;
76 nvmem-cells = <&cpu_speed_grade>;
77 nvmem-cell-names = "speed_grade";
78 cpu-idle-states = <&cpu_pd_wait>;
79 #cooling-cells = <2>;
84 compatible = "arm,cortex-a53";
86 clock-latency = <61036>;
88 enable-method = "psci";
89 i-cache-size = <0x8000>;
90 i-cache-line-size = <64>;
91 i-cache-sets = <256>;
92 d-cache-size = <0x8000>;
93 d-cache-line-size = <64>;
94 d-cache-sets = <128>;
95 next-level-cache = <&A53_L2>;
96 operating-points-v2 = <&a53_opp_table>;
97 cpu-idle-states = <&cpu_pd_wait>;
98 #cooling-cells = <2>;
103 compatible = "arm,cortex-a53";
105 clock-latency = <61036>;
107 enable-method = "psci";
108 i-cache-size = <0x8000>;
109 i-cache-line-size = <64>;
110 i-cache-sets = <256>;
111 d-cache-size = <0x8000>;
112 d-cache-line-size = <64>;
113 d-cache-sets = <128>;
114 next-level-cache = <&A53_L2>;
115 operating-points-v2 = <&a53_opp_table>;
116 cpu-idle-states = <&cpu_pd_wait>;
117 #cooling-cells = <2>;
122 compatible = "arm,cortex-a53";
124 clock-latency = <61036>;
126 enable-method = "psci";
127 i-cache-size = <0x8000>;
128 i-cache-line-size = <64>;
129 i-cache-sets = <256>;
130 d-cache-size = <0x8000>;
131 d-cache-line-size = <64>;
132 d-cache-sets = <128>;
133 next-level-cache = <&A53_L2>;
134 operating-points-v2 = <&a53_opp_table>;
135 cpu-idle-states = <&cpu_pd_wait>;
136 #cooling-cells = <2>;
139 A53_L2: l2-cache0 {
141 cache-level = <2>;
142 cache-unified;
143 cache-size = <0x80000>;
144 cache-line-size = <64>;
145 cache-sets = <512>;
149 a53_opp_table: opp-table {
150 compatible = "operating-points-v2";
151 opp-shared;
153 opp-1200000000 {
154 opp-hz = /bits/ 64 <1200000000>;
155 opp-microvolt = <850000>;
156 opp-supported-hw = <0xb00>, <0x7>;
157 clock-latency-ns = <150000>;
158 opp-suspend;
161 opp-1400000000 {
162 opp-hz = /bits/ 64 <1400000000>;
163 opp-microvolt = <950000>;
164 opp-supported-hw = <0x300>, <0x7>;
165 clock-latency-ns = <150000>;
166 opp-suspend;
169 opp-1500000000 {
170 opp-hz = /bits/ 64 <1500000000>;
171 opp-microvolt = <1000000>;
172 opp-supported-hw = <0x100>, <0x3>;
173 clock-latency-ns = <150000>;
174 opp-suspend;
178 osc_32k: clock-osc-32k {
179 compatible = "fixed-clock";
180 #clock-cells = <0>;
181 clock-frequency = <32768>;
182 clock-output-names = "osc_32k";
185 osc_24m: clock-osc-24m {
186 compatible = "fixed-clock";
187 #clock-cells = <0>;
188 clock-frequency = <24000000>;
189 clock-output-names = "osc_24m";
192 clk_ext1: clock-ext1 {
193 compatible = "fixed-clock";
194 #clock-cells = <0>;
195 clock-frequency = <133000000>;
196 clock-output-names = "clk_ext1";
199 clk_ext2: clock-ext2 {
200 compatible = "fixed-clock";
201 #clock-cells = <0>;
202 clock-frequency = <133000000>;
203 clock-output-names = "clk_ext2";
206 clk_ext3: clock-ext3 {
207 compatible = "fixed-clock";
208 #clock-cells = <0>;
209 clock-frequency = <133000000>;
210 clock-output-names = "clk_ext3";
213 clk_ext4: clock-ext4 {
214 compatible = "fixed-clock";
215 #clock-cells = <0>;
216 clock-frequency = <133000000>;
217 clock-output-names = "clk_ext4";
221 compatible = "arm,cortex-a53-pmu";
227 compatible = "arm,psci-1.0";
231 thermal-zones {
232 cpu-thermal {
233 polling-delay-passive = <250>;
234 polling-delay = <2000>;
235 thermal-sensors = <&tmu>;
250 cooling-maps {
253 cooling-device =
264 compatible = "arm,armv8-timer";
269 clock-frequency = <8000000>;
270 arm,no-tick-in-suspend;
274 compatible = "fsl,imx8mn-soc", "simple-bus";
275 #address-cells = <1>;
276 #size-cells = <1>;
278 dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>;
279 nvmem-cells = <&imx8mn_uid>;
280 nvmem-cell-names = "soc_unique_id";
283 compatible = "fsl,aips-bus", "simple-bus";
285 #address-cells = <1>;
286 #size-cells = <1>;
289 spba2: spba-bus@30000000 {
290 compatible = "fsl,spba-bus", "simple-bus";
291 #address-cells = <1>;
292 #size-cells = <1>;
297 compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai";
299 #sound-dai-cells = <0>;
305 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
307 dma-names = "rx", "tx";
312 compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai";
314 #sound-dai-cells = <0>;
320 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
322 dma-names = "rx", "tx";
327 compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai";
329 #sound-dai-cells = <0>;
335 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
337 dma-names = "rx", "tx";
338 fsl,shared-interrupt;
344 compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai";
346 #sound-dai-cells = <0>;
352 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
354 dma-names = "rx", "tx";
358 micfil: audio-controller@30080000 {
359 compatible = "fsl,imx8mm-micfil";
370 clock-names = "ipg_clk", "ipg_clk_app",
373 dma-names = "rx";
374 #sound-dai-cells = <0>;
379 compatible = "fsl,imx35-spdif";
392 clock-names = "core", "rxtx0",
398 dma-names = "rx", "tx";
403 compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai";
405 #sound-dai-cells = <0>;
411 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
413 dma-names = "rx", "tx";
418 compatible = "fsl,imx8mn-easrc";
422 clock-names = "mem";
427 dma-names = "ctx0_rx", "ctx0_tx",
431 firmware-name = "imx/easrc/easrc-imx8mn.bin";
432 fsl,asrc-rate = <8000>;
433 fsl,asrc-format = <2>;
439 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
444 gpio-controller;
445 #gpio-cells = <2>;
446 interrupt-controller;
447 #interrupt-cells = <2>;
448 gpio-ranges = <&iomuxc 0 10 30>;
452 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
457 gpio-controller;
458 #gpio-cells = <2>;
459 interrupt-controller;
460 #interrupt-cells = <2>;
461 gpio-ranges = <&iomuxc 0 40 21>;
465 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
470 gpio-controller;
471 #gpio-cells = <2>;
472 interrupt-controller;
473 #interrupt-cells = <2>;
474 gpio-ranges = <&iomuxc 0 61 26>;
478 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
483 gpio-controller;
484 #gpio-cells = <2>;
485 interrupt-controller;
486 #interrupt-cells = <2>;
487 gpio-ranges = <&iomuxc 21 108 11>;
491 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
496 gpio-controller;
497 #gpio-cells = <2>;
498 interrupt-controller;
499 #interrupt-cells = <2>;
500 gpio-ranges = <&iomuxc 0 119 30>;
504 compatible = "fsl,imx8mn-tmu", "fsl,imx8mm-tmu";
507 nvmem-cells = <&tmu_calib>;
508 nvmem-cell-names = "calib";
509 #thermal-sensor-cells = <0>;
513 compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt";
521 compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt";
529 compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt";
536 sdma3: dma-controller@302b0000 {
537 compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma";
542 clock-names = "ipg", "ahb";
543 #dma-cells = <3>;
544 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
547 sdma2: dma-controller@302c0000 {
548 compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma";
553 clock-names = "ipg", "ahb";
554 #dma-cells = <3>;
555 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
559 compatible = "fsl,imx8mn-iomuxc";
564 compatible = "fsl,imx8mn-iomuxc-gpr", "syscon";
569 compatible = "fsl,imx8mn-ocotp", "fsl,imx8mm-ocotp", "syscon";
572 #address-cells = <1>;
573 #size-cells = <1>;
581 * Fuse Address = (ADDR * 4) + 0x400
583 * each subsequent fuse is located at offset
588 imx8mn_uid: unique-id@4 { /* 0x410-0x420 */
592 cpu_speed_grade: speed-grade@10 { /* 0x440 */
600 fec_mac_address: mac-address@90 { /* 0x640 */
605 anatop: clock-controller@30360000 {
606 compatible = "fsl,imx8mn-anatop", "fsl,imx8mm-anatop";
608 #clock-cells = <1>;
612 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
615 snvs_rtc: snvs-rtc-lp {
616 compatible = "fsl,sec-v4.0-mon-rtc-lp";
622 clock-names = "snvs-rtc";
625 snvs_pwrkey: snvs-powerkey {
626 compatible = "fsl,sec-v4.0-pwrkey";
630 clock-names = "snvs-pwrkey";
632 wakeup-source;
637 clk: clock-controller@30380000 {
638 compatible = "fsl,imx8mn-ccm";
642 #clock-cells = <1>;
645 clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
647 assigned-clocks = <&clk IMX8MN_CLK_A53_SRC>,
655 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_800M>,
659 assigned-clock-rates = <0>, <0>, <0>,
667 src: reset-controller@30390000 {
668 compatible = "fsl,imx8mn-src", "fsl,imx8mq-src", "syscon";
671 #reset-cells = <1>;
675 compatible = "fsl,imx8mn-gpc";
677 interrupt-parent = <&gic>;
681 #address-cells = <1>;
682 #size-cells = <0>;
684 pgc_hsiomix: power-domain@0 {
685 #power-domain-cells = <0>;
690 pgc_otg1: power-domain@1 {
691 #power-domain-cells = <0>;
695 pgc_gpumix: power-domain@2 {
696 #power-domain-cells = <0>;
704 pgc_dispmix: power-domain@3 {
705 #power-domain-cells = <0>;
711 pgc_mipi: power-domain@4 {
712 #power-domain-cells = <0>;
714 power-domains = <&pgc_dispmix>;
721 compatible = "fsl,aips-bus", "simple-bus";
723 #address-cells = <1>;
724 #size-cells = <1>;
728 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm";
733 clock-names = "ipg", "per";
734 #pwm-cells = <3>;
739 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm";
744 clock-names = "ipg", "per";
745 #pwm-cells = <3>;
750 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm";
755 clock-names = "ipg", "per";
756 #pwm-cells = <3>;
761 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm";
766 clock-names = "ipg", "per";
767 #pwm-cells = <3>;
772 compatible = "nxp,sysctr-timer";
776 clock-names = "per";
781 compatible = "fsl,aips-bus", "simple-bus";
783 #address-cells = <1>;
784 #size-cells = <1>;
787 spba1: spba-bus@30800000 {
788 compatible = "fsl,spba-bus", "simple-bus";
789 #address-cells = <1>;
790 #size-cells = <1>;
795 compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi";
796 #address-cells = <1>;
797 #size-cells = <0>;
802 clock-names = "ipg", "per";
804 dma-names = "rx", "tx";
809 compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi";
810 #address-cells = <1>;
811 #size-cells = <0>;
816 clock-names = "ipg", "per";
818 dma-names = "rx", "tx";
823 compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi";
824 #address-cells = <1>;
825 #size-cells = <0>;
830 clock-names = "ipg", "per";
832 dma-names = "rx", "tx";
837 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
842 clock-names = "ipg", "per";
844 dma-names = "rx", "tx";
849 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
854 clock-names = "ipg", "per";
856 dma-names = "rx", "tx";
861 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
866 clock-names = "ipg", "per";
872 compatible = "fsl,sec-v4.0";
873 #address-cells = <1>;
874 #size-cells = <1>;
880 clock-names = "aclk", "ipg";
883 compatible = "fsl,sec-v4.0-job-ring";
890 compatible = "fsl,sec-v4.0-job-ring";
896 compatible = "fsl,sec-v4.0-job-ring";
903 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c";
904 #address-cells = <1>;
905 #size-cells = <0>;
913 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c";
914 #address-cells = <1>;
915 #size-cells = <0>;
923 #address-cells = <1>;
924 #size-cells = <0>;
925 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c";
933 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c";
934 #address-cells = <1>;
935 #size-cells = <0>;
943 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
948 clock-names = "ipg", "per";
950 dma-names = "rx", "tx";
955 compatible = "fsl,imx8mn-mu", "fsl,imx6sx-mu";
959 #mbox-cells = <2>;
963 compatible = "fsl,imx8mn-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
969 clock-names = "ipg", "ahb", "per";
970 fsl,tuning-start-tap = <20>;
971 fsl,tuning-step = <2>;
972 bus-width = <4>;
977 compatible = "fsl,imx8mn-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
983 clock-names = "ipg", "ahb", "per";
984 fsl,tuning-start-tap = <20>;
985 fsl,tuning-step = <2>;
986 bus-width = <4>;
991 compatible = "fsl,imx8mn-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
997 clock-names = "ipg", "ahb", "per";
998 fsl,tuning-start-tap = <20>;
999 fsl,tuning-step = <2>;
1000 bus-width = <4>;
1005 #address-cells = <1>;
1006 #size-cells = <0>;
1007 compatible = "nxp,imx8mm-fspi";
1009 reg-names = "fspi_base", "fspi_mmap";
1013 clock-names = "fspi_en", "fspi";
1017 sdma1: dma-controller@30bd0000 {
1018 compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma";
1023 clock-names = "ipg", "ahb";
1024 #dma-cells = <3>;
1025 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
1029 compatible = "fsl,imx8mn-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec";
1040 clock-names = "ipg", "ahb", "ptp",
1042 assigned-clocks = <&clk IMX8MN_CLK_ENET_AXI>,
1046 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_266M>,
1050 assigned-clock-rates = <0>, <100000000>, <125000000>, <0>;
1051 fsl,num-tx-queues = <3>;
1052 fsl,num-rx-queues = <3>;
1053 nvmem-cells = <&fec_mac_address>;
1054 nvmem-cell-names = "mac-address";
1055 fsl,stop-mode = <&gpr 0x10 3>;
1062 compatible = "fsl,aips-bus", "simple-bus";
1064 #address-cells = <1>;
1065 #size-cells = <1>;
1069 compatible = "fsl,imx8mn-lcdif", "fsl,imx6sx-lcdif";
1074 clock-names = "pix", "axi", "disp_axi";
1076 power-domains = <&disp_blk_ctrl IMX8MN_DISPBLK_PD_LCDIF>;
1081 remote-endpoint = <&dsim_from_lcdif>;
1087 compatible = "fsl,imx8mn-mipi-dsim", "fsl,imx8mm-mipi-dsim";
1091 clock-names = "bus_clk", "sclk_mipi";
1093 power-domains = <&disp_blk_ctrl IMX8MN_DISPBLK_PD_MIPI_DSI>;
1097 #address-cells = <1>;
1098 #size-cells = <0>;
1104 remote-endpoint = <&lcdif_to_dsim>;
1118 compatible = "fsl,imx8mn-isi";
1123 clock-names = "axi", "apb";
1124 fsl,blk-ctrl = <&disp_blk_ctrl>;
1125 power-domains = <&disp_blk_ctrl IMX8MN_DISPBLK_PD_ISI>;
1129 #address-cells = <1>;
1130 #size-cells = <0>;
1135 remote-endpoint = <&mipi_csi_out>;
1141 disp_blk_ctrl: blk-ctrl@32e28000 {
1142 compatible = "fsl,imx8mn-disp-blk-ctrl", "syscon";
1144 power-domains = <&pgc_dispmix>, <&pgc_dispmix>,
1147 power-domain-names = "bus", "isi",
1148 "lcdif", "mipi-dsi",
1149 "mipi-csi";
1161 clock-names = "disp_axi", "disp_apb",
1163 "lcdif-axi", "lcdif-apb", "lcdif-pix",
1164 "dsi-pclk", "dsi-ref",
1165 "csi-aclk", "csi-pclk";
1166 assigned-clocks = <&clk IMX8MN_CLK_DSI_CORE>,
1171 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_266M>,
1176 assigned-clock-rates = <266000000>,
1181 #power-domain-cells = <1>;
1184 mipi_csi: mipi-csi@32e30000 {
1185 compatible = "fsl,imx8mm-mipi-csi2";
1188 assigned-clocks = <&clk IMX8MN_CLK_CAMERA_PIXEL>;
1189 assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_1000M>;
1190 assigned-clock-rates = <333000000>;
1191 clock-frequency = <333000000>;
1196 clock-names = "pclk", "wrap", "phy", "axi";
1197 power-domains = <&disp_blk_ctrl IMX8MN_DISPBLK_PD_MIPI_CSI>;
1201 #address-cells = <1>;
1202 #size-cells = <0>;
1212 remote-endpoint = <&isi_in>;
1219 compatible = "fsl,imx8mn-usb", "fsl,imx7d-usb", "fsl,imx27-usb";
1223 assigned-clocks = <&clk IMX8MN_CLK_USB_BUS>;
1224 assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_500M>;
1227 power-domains = <&pgc_hsiomix>;
1232 compatible = "fsl,imx8mn-usbmisc", "fsl,imx7d-usbmisc",
1233 "fsl,imx6q-usbmisc";
1234 #index-cells = <1>;
1239 dma_apbh: dma-controller@33000000 {
1240 compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh";
1246 #dma-cells = <1>;
1247 dma-channels = <4>;
1251 gpmi: nand-controller@33002000 {
1252 compatible = "fsl,imx8mn-gpmi-nand", "fsl,imx7d-gpmi-nand";
1253 #address-cells = <1>;
1254 #size-cells = <0>;
1256 reg-names = "gpmi-nand", "bch";
1258 interrupt-names = "bch";
1261 clock-names = "gpmi_io", "gpmi_bch_apb";
1263 dma-names = "rx-tx";
1275 clock-names = "reg", "bus", "core", "shader";
1276 assigned-clocks = <&clk IMX8MN_CLK_GPU_CORE>,
1281 assigned-clock-parents = <&clk IMX8MN_GPU_PLL_OUT>,
1285 assigned-clock-rates = <400000000>,
1290 power-domains = <&pgc_gpumix>;
1293 gic: interrupt-controller@38800000 {
1294 compatible = "arm,gic-v3";
1297 #interrupt-cells = <3>;
1298 interrupt-controller;
1302 ddrc: memory-controller@3d400000 {
1303 compatible = "fsl,imx8mn-ddrc", "fsl,imx8m-ddrc";
1305 clock-names = "core", "pll", "alt", "apb";
1312 ddr-pmu@3d800000 {
1313 compatible = "fsl,imx8mn-ddr-pmu", "fsl,imx8m-ddr-pmu";
1320 #phy-cells = <0>;
1321 compatible = "usb-nop-xceiv";
1323 assigned-clocks = <&clk IMX8MN_CLK_USB_PHY_REF>;
1324 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_100M>;
1325 clock-names = "main_clk";
1326 power-domains = <&pgc_otg1>;