Lines Matching +full:opp +full:- +full:fuse +full:- +full:level
1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra30-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra30-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/soc/tegra-pmc.h>
8 #include <dt-bindings/thermal/thermal.h>
10 #include "tegra30-peripherals-opp.dtsi"
14 interrupt-parent = <&lic>;
15 #address-cells = <1>;
16 #size-cells = <1>;
24 compatible = "nvidia,tegra30-pcie";
29 reg-names = "pads", "afi", "cs";
32 interrupt-names = "intr", "msi";
34 #interrupt-cells = <1>;
35 interrupt-map-mask = <0 0 0 0>;
36 interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
38 bus-range = <0x00 0xff>;
39 #address-cells = <3>;
40 #size-cells = <2>;
46 <0x02000000 0 0x20000000 0x20000000 0 0x08000000>, /* non-prefetchable memory */
53 clock-names = "pex", "afi", "pll_e", "cml";
57 reset-names = "pex", "afi", "pcie_x";
58 power-domains = <&pd_core>;
59 operating-points-v2 = <&pcie_dvfs_opp_table>;
64 assigned-addresses = <0x82000800 0 0x00000000 0 0x1000>;
66 bus-range = <0x00 0xff>;
69 #address-cells = <3>;
70 #size-cells = <2>;
73 nvidia,num-lanes = <2>;
78 assigned-addresses = <0x82001000 0 0x00001000 0 0x1000>;
80 bus-range = <0x00 0xff>;
83 #address-cells = <3>;
84 #size-cells = <2>;
87 nvidia,num-lanes = <2>;
92 assigned-addresses = <0x82001800 0 0x00004000 0 0x1000>;
94 bus-range = <0x00 0xff>;
97 #address-cells = <3>;
98 #size-cells = <2>;
101 nvidia,num-lanes = <2>;
106 compatible = "mmio-sram";
108 #address-cells = <1>;
109 #size-cells = <1>;
119 compatible = "nvidia,tegra30-host1x";
123 interrupt-names = "syncpt", "host1x";
125 clock-names = "host1x";
127 reset-names = "host1x", "mc";
129 power-domains = <&pd_heg>;
130 operating-points-v2 = <&host1x_dvfs_opp_table>;
132 #address-cells = <1>;
133 #size-cells = <1>;
138 compatible = "nvidia,tegra30-mpe";
143 reset-names = "mpe";
144 power-domains = <&pd_mpe>;
145 operating-points-v2 = <&mpe_dvfs_opp_table>;
153 compatible = "nvidia,tegra30-vi";
158 reset-names = "vi";
159 power-domains = <&pd_venc>;
160 operating-points-v2 = <&vi_dvfs_opp_table>;
168 compatible = "nvidia,tegra30-epp";
173 reset-names = "epp";
174 power-domains = <&pd_heg>;
175 operating-points-v2 = <&epp_dvfs_opp_table>;
183 compatible = "nvidia,tegra30-isp";
188 reset-names = "isp";
189 power-domains = <&pd_venc>;
197 compatible = "nvidia,tegra30-gr2d";
202 reset-names = "2d", "mc";
203 power-domains = <&pd_heg>;
204 operating-points-v2 = <&gr2d_dvfs_opp_table>;
210 compatible = "nvidia,tegra30-gr3d";
214 clock-names = "3d", "3d2";
219 reset-names = "3d", "3d2", "mc", "mc2";
220 power-domains = <&pd_3d0>, <&pd_3d1>;
221 power-domain-names = "3d0", "3d1";
222 operating-points-v2 = <&gr3d_dvfs_opp_table>;
229 compatible = "nvidia,tegra30-dc";
234 clock-names = "dc", "parent";
236 reset-names = "dc";
237 power-domains = <&pd_core>;
238 operating-points-v2 = <&disp1_dvfs_opp_table>;
249 interconnect-names = "wina",
251 "winb-vfilter",
261 compatible = "nvidia,tegra30-dc";
266 clock-names = "dc", "parent";
268 reset-names = "dc";
269 power-domains = <&pd_core>;
270 operating-points-v2 = <&disp2_dvfs_opp_table>;
281 interconnect-names = "wina",
283 "winb-vfilter",
293 compatible = "nvidia,tegra30-hdmi";
298 clock-names = "hdmi", "parent";
300 reset-names = "hdmi";
301 power-domains = <&pd_core>;
302 operating-points-v2 = <&hdmi_dvfs_opp_table>;
307 compatible = "nvidia,tegra30-tvo";
311 power-domains = <&pd_core>;
312 operating-points-v2 = <&tvo_dvfs_opp_table>;
317 compatible = "nvidia,tegra30-dsi";
321 clock-names = "dsi", "parent";
323 reset-names = "dsi";
324 power-domains = <&pd_core>;
325 operating-points-v2 = <&dsia_dvfs_opp_table>;
330 compatible = "nvidia,tegra30-dsi";
334 clock-names = "dsi", "parent";
336 reset-names = "dsi";
337 power-domains = <&pd_core>;
338 operating-points-v2 = <&dsib_dvfs_opp_table>;
344 compatible = "arm,cortex-a9-twd-timer";
346 interrupt-parent = <&intc>;
352 intc: interrupt-controller@50041000 {
353 compatible = "arm,cortex-a9-gic";
356 interrupt-controller;
357 #interrupt-cells = <3>;
358 interrupt-parent = <&intc>;
361 cache-controller@50043000 {
362 compatible = "arm,pl310-cache";
364 arm,data-latency = <6 6 2>;
365 arm,tag-latency = <5 5 2>;
366 cache-unified;
367 cache-level = <2>;
370 lic: interrupt-controller@60004000 {
371 compatible = "nvidia,tegra30-ictlr";
377 interrupt-controller;
378 #interrupt-cells = <3>;
379 interrupt-parent = <&intc>;
383 compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";
395 compatible = "nvidia,tegra30-car";
397 #clock-cells = <1>;
398 #reset-cells = <1>;
400 pll-c {
401 compatible = "nvidia,tegra30-pllc";
403 power-domains = <&pd_core>;
404 operating-points-v2 = <&pll_c_dvfs_opp_table>;
407 pll-e {
408 compatible = "nvidia,tegra30-plle";
410 power-domains = <&pd_core>;
411 operating-points-v2 = <&pll_e_dvfs_opp_table>;
414 pll-m {
415 compatible = "nvidia,tegra30-pllm";
417 power-domains = <&pd_core>;
418 operating-points-v2 = <&pll_m_dvfs_opp_table>;
422 compatible = "nvidia,tegra30-sclk";
424 power-domains = <&pd_core>;
425 operating-points-v2 = <&sclk_dvfs_opp_table>;
429 flow-controller@60007000 {
430 compatible = "nvidia,tegra30-flowctrl";
435 compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
471 reset-names = "dma";
472 #dma-cells = <1>;
476 compatible = "nvidia,tegra30-ahb";
481 compatible = "nvidia,tegra30-actmon";
486 clock-names = "actmon", "emc";
488 reset-names = "actmon";
489 operating-points-v2 = <&emc_bw_dfs_opp_table>;
491 interconnect-names = "cpu-read";
492 #cooling-cells = <2>;
496 compatible = "nvidia,tegra30-gpio";
506 #gpio-cells = <2>;
507 gpio-controller;
508 #interrupt-cells = <2>;
509 interrupt-controller;
510 gpio-ranges = <&pinmux 0 0 248>;
514 compatible = "nvidia,tegra30-vde", "nvidia,tegra20-vde";
518 <0x6001c200 0x100>, /* Post-processing Engine */
524 reg-names = "sxe", "bsev", "mbe", "ppe", "mce",
528 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, /* BSE-V interrupt */
530 interrupt-names = "sync-token", "bsev", "sxe";
532 reset-names = "vde", "mc";
535 power-domains = <&pd_vde>;
536 operating-points-v2 = <&vde_dvfs_opp_table>;
540 compatible = "nvidia,tegra30-apbmisc", "nvidia,tegra20-apbmisc";
546 compatible = "nvidia,tegra30-pinmux";
555 * is "nvidia,tegra30-uart", "nvidia,tegra20-uart" and to enable
557 * "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart".
560 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
562 reg-shift = <2>;
567 dma-names = "rx", "tx";
572 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
574 reg-shift = <2>;
579 dma-names = "rx", "tx";
584 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
586 reg-shift = <2>;
591 dma-names = "rx", "tx";
596 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
598 reg-shift = <2>;
603 dma-names = "rx", "tx";
608 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
610 reg-shift = <2>;
615 dma-names = "rx", "tx";
620 compatible = "nvidia,tegra30-gmi";
622 #address-cells = <2>;
623 #size-cells = <1>;
626 clock-names = "gmi";
628 reset-names = "gmi";
629 power-domains = <&pd_core>;
630 operating-points-v2 = <&nor_dvfs_opp_table>;
635 compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm";
637 #pwm-cells = <2>;
640 reset-names = "pwm";
641 power-domains = <&pd_core>;
642 operating-points-v2 = <&pwm_dvfs_opp_table>;
647 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
650 #address-cells = <1>;
651 #size-cells = <0>;
654 clock-names = "div-clk", "fast-clk";
656 reset-names = "i2c";
658 dma-names = "rx", "tx";
663 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
666 #address-cells = <1>;
667 #size-cells = <0>;
670 clock-names = "div-clk", "fast-clk";
672 reset-names = "i2c";
674 dma-names = "rx", "tx";
679 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
682 #address-cells = <1>;
683 #size-cells = <0>;
686 clock-names = "div-clk", "fast-clk";
688 reset-names = "i2c";
690 dma-names = "rx", "tx";
695 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
698 #address-cells = <1>;
699 #size-cells = <0>;
703 reset-names = "i2c";
704 clock-names = "div-clk", "fast-clk";
706 dma-names = "rx", "tx";
711 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
714 #address-cells = <1>;
715 #size-cells = <0>;
718 clock-names = "div-clk", "fast-clk";
720 reset-names = "i2c";
722 dma-names = "rx", "tx";
727 compatible = "nvidia,tegra30-slink";
730 #address-cells = <1>;
731 #size-cells = <0>;
734 reset-names = "spi";
736 dma-names = "rx", "tx";
737 power-domains = <&pd_core>;
738 operating-points-v2 = <&sbc1_dvfs_opp_table>;
743 compatible = "nvidia,tegra30-slink";
746 #address-cells = <1>;
747 #size-cells = <0>;
750 reset-names = "spi";
752 dma-names = "rx", "tx";
753 power-domains = <&pd_core>;
754 operating-points-v2 = <&sbc2_dvfs_opp_table>;
759 compatible = "nvidia,tegra30-slink";
762 #address-cells = <1>;
763 #size-cells = <0>;
766 reset-names = "spi";
768 dma-names = "rx", "tx";
769 power-domains = <&pd_core>;
770 operating-points-v2 = <&sbc3_dvfs_opp_table>;
775 compatible = "nvidia,tegra30-slink";
778 #address-cells = <1>;
779 #size-cells = <0>;
782 reset-names = "spi";
784 dma-names = "rx", "tx";
785 power-domains = <&pd_core>;
786 operating-points-v2 = <&sbc4_dvfs_opp_table>;
791 compatible = "nvidia,tegra30-slink";
794 #address-cells = <1>;
795 #size-cells = <0>;
798 reset-names = "spi";
800 dma-names = "rx", "tx";
801 power-domains = <&pd_core>;
802 operating-points-v2 = <&sbc5_dvfs_opp_table>;
807 compatible = "nvidia,tegra30-slink";
810 #address-cells = <1>;
811 #size-cells = <0>;
814 reset-names = "spi";
816 dma-names = "rx", "tx";
817 power-domains = <&pd_core>;
818 operating-points-v2 = <&sbc6_dvfs_opp_table>;
823 compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc";
830 compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc";
835 reset-names = "kbc";
840 compatible = "nvidia,tegra30-pmc";
843 clock-names = "pclk", "clk32k_in";
844 #clock-cells = <1>;
846 pd_core: core-domain {
847 #power-domain-cells = <0>;
848 operating-points-v2 = <&core_opp_table>;
862 power-domains = <&pd_core>;
863 #power-domain-cells = <0>;
870 power-domains = <&pd_core>;
871 #power-domain-cells = <0>;
878 power-domains = <&pd_core>;
879 #power-domain-cells = <0>;
886 power-domains = <&pd_core>;
887 #power-domain-cells = <0>;
894 power-domains = <&pd_core>;
895 #power-domain-cells = <0>;
907 power-domains = <&pd_core>;
908 #power-domain-cells = <0>;
913 mc: memory-controller@7000f000 {
914 compatible = "nvidia,tegra30-mc";
917 clock-names = "mc";
921 #iommu-cells = <1>;
922 #reset-cells = <1>;
923 #interconnect-cells = <1>;
926 emc: memory-controller@7000f400 {
927 compatible = "nvidia,tegra30-emc";
931 power-domains = <&pd_core>;
933 nvidia,memory-controller = <&mc>;
934 operating-points-v2 = <&emc_icc_dvfs_opp_table>;
936 #interconnect-cells = <0>;
939 fuse@7000f800 {
940 compatible = "nvidia,tegra30-efuse";
943 clock-names = "fuse";
945 reset-names = "fuse";
946 power-domains = <&pd_core>;
947 operating-points-v2 = <&fuse_burn_dvfs_opp_table>;
951 compatible = "nvidia,tegra30-tsensor";
957 assigned-clocks = <&tegra_car TEGRA30_CLK_TSENSOR>;
958 assigned-clock-parents = <&tegra_car TEGRA30_CLK_CLK_M>;
959 assigned-clock-rates = <500000>;
961 #thermal-sensor-cells = <1>;
965 compatible = "nvidia,tegra30-hda";
971 clock-names = "hda", "hda2hdmi", "hda2codec_2x";
975 reset-names = "hda", "hda2hdmi", "hda2codec_2x";
980 compatible = "nvidia,tegra30-ahub";
986 clock-names = "d_audio", "apbif";
998 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
1005 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
1008 #address-cells = <1>;
1009 #size-cells = <1>;
1012 compatible = "nvidia,tegra30-i2s";
1014 nvidia,ahub-cif-ids = <4 4>;
1017 reset-names = "i2s";
1022 compatible = "nvidia,tegra30-i2s";
1024 nvidia,ahub-cif-ids = <5 5>;
1027 reset-names = "i2s";
1032 compatible = "nvidia,tegra30-i2s";
1034 nvidia,ahub-cif-ids = <6 6>;
1037 reset-names = "i2s";
1042 compatible = "nvidia,tegra30-i2s";
1044 nvidia,ahub-cif-ids = <7 7>;
1047 reset-names = "i2s";
1052 compatible = "nvidia,tegra30-i2s";
1054 nvidia,ahub-cif-ids = <8 8>;
1057 reset-names = "i2s";
1063 compatible = "nvidia,tegra30-sdhci";
1067 clock-names = "sdhci";
1069 reset-names = "sdhci";
1070 power-domains = <&pd_core>;
1071 operating-points-v2 = <&sdmmc1_dvfs_opp_table>;
1076 compatible = "nvidia,tegra30-sdhci";
1080 clock-names = "sdhci";
1082 reset-names = "sdhci";
1087 compatible = "nvidia,tegra30-sdhci";
1091 clock-names = "sdhci";
1093 reset-names = "sdhci";
1094 power-domains = <&pd_core>;
1095 operating-points-v2 = <&sdmmc3_dvfs_opp_table>;
1100 compatible = "nvidia,tegra30-sdhci";
1104 clock-names = "sdhci";
1106 reset-names = "sdhci";
1111 compatible = "nvidia,tegra30-ehci";
1117 reset-names = "usb";
1118 nvidia,needs-double-reset;
1120 power-domains = <&pd_core>;
1121 operating-points-v2 = <&usbd_dvfs_opp_table>;
1125 phy1: usb-phy@7d000000 {
1126 compatible = "nvidia,tegra30-usb-phy";
1134 clock-names = "reg", "pll_u", "utmi-pads";
1136 reset-names = "usb", "utmi-pads";
1137 #phy-cells = <0>;
1138 nvidia,hssync-start-delay = <9>;
1139 nvidia,idle-wait-delay = <17>;
1140 nvidia,elastic-limit = <16>;
1141 nvidia,term-range-adj = <6>;
1142 nvidia,xcvr-setup = <51>;
1143 nvidia,xcvr-setup-use-fuses;
1144 nvidia,xcvr-lsfslew = <1>;
1145 nvidia,xcvr-lsrslew = <1>;
1146 nvidia,xcvr-hsslew = <32>;
1147 nvidia,hssquelch-level = <2>;
1148 nvidia,hsdiscon-level = <5>;
1149 nvidia,has-utmi-pad-registers;
1155 compatible = "nvidia,tegra30-ehci";
1161 reset-names = "usb";
1163 power-domains = <&pd_core>;
1164 operating-points-v2 = <&usb2_dvfs_opp_table>;
1168 phy2: usb-phy@7d004000 {
1169 compatible = "nvidia,tegra30-usb-phy";
1177 clock-names = "reg", "pll_u", "utmi-pads";
1179 reset-names = "usb", "utmi-pads";
1180 #phy-cells = <0>;
1181 nvidia,hssync-start-delay = <9>;
1182 nvidia,idle-wait-delay = <17>;
1183 nvidia,elastic-limit = <16>;
1184 nvidia,term-range-adj = <6>;
1185 nvidia,xcvr-setup = <51>;
1186 nvidia,xcvr-setup-use-fuses;
1187 nvidia,xcvr-lsfslew = <2>;
1188 nvidia,xcvr-lsrslew = <2>;
1189 nvidia,xcvr-hsslew = <32>;
1190 nvidia,hssquelch-level = <2>;
1191 nvidia,hsdiscon-level = <5>;
1197 compatible = "nvidia,tegra30-ehci";
1203 reset-names = "usb";
1205 power-domains = <&pd_core>;
1206 operating-points-v2 = <&usb3_dvfs_opp_table>;
1210 phy3: usb-phy@7d008000 {
1211 compatible = "nvidia,tegra30-usb-phy";
1219 clock-names = "reg", "pll_u", "utmi-pads";
1221 reset-names = "usb", "utmi-pads";
1222 #phy-cells = <0>;
1223 nvidia,hssync-start-delay = <0>;
1224 nvidia,idle-wait-delay = <17>;
1225 nvidia,elastic-limit = <16>;
1226 nvidia,term-range-adj = <6>;
1227 nvidia,xcvr-setup = <51>;
1228 nvidia,xcvr-setup-use-fuses;
1229 nvidia,xcvr-lsfslew = <2>;
1230 nvidia,xcvr-lsrslew = <2>;
1231 nvidia,xcvr-hsslew = <32>;
1232 nvidia,hssquelch-level = <2>;
1233 nvidia,hsdiscon-level = <5>;
1239 #address-cells = <1>;
1240 #size-cells = <0>;
1244 compatible = "arm,cortex-a9";
1247 #cooling-cells = <2>;
1252 compatible = "arm,cortex-a9";
1255 #cooling-cells = <2>;
1260 compatible = "arm,cortex-a9";
1263 #cooling-cells = <2>;
1268 compatible = "arm,cortex-a9";
1271 #cooling-cells = <2>;
1276 compatible = "arm,cortex-a9-pmu";
1281 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
1284 thermal-zones {
1285 tsensor0-thermal {
1286 polling-delay-passive = <1000>; /* milliseconds */
1287 polling-delay = <5000>; /* milliseconds */
1289 thermal-sensors = <&tsensor 0>;
1292 level1_trip: dvfs-alert {
1299 level2_trip: cpu-div2-throttle {
1306 level3_trip: soc-critical {
1314 cooling-maps {
1317 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1326 tsensor1-thermal {
1329 polling-delay-passive = <1000>; /* milliseconds */
1330 polling-delay = <0>; /* milliseconds */
1332 thermal-sensors = <&tsensor 1>;
1335 dvfs-alert {