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/linux/Documentation/devicetree/bindings/opp/
H A Dopp-v2.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/opp/opp-v2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Generic OPP (Operating Performance Points)
10 - Viresh Kumar <viresh.kumar@linaro.org>
13 - $ref: opp-v2-base.yaml#
17 const: operating-points-v2
22 - |
24 * Example 1: Single cluster Dual-core ARM cortex A9, switch DVFS states
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H A Dopp-v2-base.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/opp/opp-v2-base.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Generic OPP (Operating Performance Points) Common Properties
10 - Viresh Kumar <viresh.kumar@linaro.org>
13 Devices work at voltage-current-frequency combinations and some implementations
25 pattern: '^opp-table(-[a-z0-9]+)?$'
27 opp-shared:
29 Indicates that device nodes using this OPP Table Node's phandle switch
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H A Dopp-v2-kryo-cpu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/opp/opp-v2-kryo-cpu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Technologies, Inc. NVMEM OPP
10 - Ilia Lin <ilia.lin@kernel.org>
13 - $ref: opp-v2-base.yaml#
17 the CPU frequencies subset and voltage value of each OPP varies based on
22 The qcom-cpufreq-nvmem driver reads the efuse value from the SoC to provide
23 the OPP framework with required information (existing HW bitmap).
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H A Dopp-v2-qcom-level.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/opp/opp-v2-qcom-level.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm OPP
10 - Niklas Cassel <nks@flawful.org>
13 - $ref: opp-v2-base.yaml#
17 const: operating-points-v2-qcom-level
20 '^opp-?[0-9]+$':
25 opp-level: true
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H A Dti,omap-opp-supply.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/opp/ti,omap-opp-supply.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Texas Instruments OMAP compatible OPP supply
11 registers, which contain OPP-specific voltage information tailored
14 the primary regulator during an OPP transition.
16 Also, some supplies may have an associated vbb-supply, an Adaptive
18 w.r.t the vdd-supply and clk when making an OPP transition. By
19 supplying two regulators to the device that will undergo OPP
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/linux/arch/powerpc/kvm/
H A Dmpic.c47 #define OPENPIC_FLAG_IDR_CRIT (1 << 0)
63 #define OPENPIC_CPU_REG_SIZE (0x100 + ((MAX_CPU - 1) * 0x1000))
95 #define IDR_EP_MASK (1 << IDR_EP_SHIFT)
98 #define IDR_P1_SHIFT 1
116 struct kvm_vcpu *vcpu = current->thread.kvm_vcpu; in get_current_cpu()
117 return vcpu ? vcpu->arch.irq_cpu_id : -1; in get_current_cpu()
120 return -1; in get_current_cpu()
128 static inline void write_IRQreg_idr(struct openpic *opp, int n_IRQ,
133 IRQ_TYPE_FSLINT, /* FSL internal interrupt -- level only */
154 bool level:1; /* level-triggered */
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/linux/Documentation/power/
H A Dopp.rst2 Operating Performance Points (OPP) Library
5 (C) 2009-2010 Nishanth Menon <nm@ti.com>, Texas Instruments Incorporated
9 1. Introduction
10 2. Initial OPP List Registration
11 3. OPP Search Functions
12 4. OPP Availability Control Functions
13 5. OPP Data Retrieval Functions
16 1. Introduction
19 1.1 What is an Operating Performance Point (OPP)?
20 -------------------------------------------------
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/linux/drivers/opp/
H A Dcore.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Generic OPP Interface
5 * Copyright (C) 2009-2010 Texas Instruments Incorporated.
23 #include "opp.h"
26 * The root of the list of all opp-tables. All opp_table structures branch off
32 /* Lock to allow exclusive modification to the device and opp lists */
37 /* OPP ID allocator */
45 mutex_lock(&opp_table->lock); in _find_opp_dev()
46 list_for_each_entry(opp_dev, &opp_table->dev_list, node) in _find_opp_dev()
47 if (opp_dev->dev == dev) { in _find_opp_dev()
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/linux/arch/arm/boot/dts/samsung/
H A Dexynos4x12.dtsi1 // SPDX-License-Identifier: GPL-2.0
19 #include "exynos4-cpu-thermal.dtsi"
27 fimc-lite0 = &fimc_lite_0;
28 fimc-lite1 = &fimc_lite_1;
31 bus_acp: bus-acp {
32 compatible = "samsung,exynos-bus";
34 clock-names = "bus";
35 operating-points-v2 = <&bus_acp_opp_table>;
38 bus_acp_opp_table: opp-table {
39 compatible = "operating-points-v2";
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H A Dexynos4210.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
7 * Copyright (c) 2010-2011 Linaro Ltd.
20 #include "exynos4-cpu-thermal.dtsi"
31 bus_acp: bus-acp {
32 compatible = "samsung,exynos-bus";
34 clock-names = "bus";
35 operating-points-v2 = <&bus_acp_opp_table>;
38 bus_acp_opp_table: opp-table {
39 compatible = "operating-points-v2";
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/linux/Documentation/devicetree/bindings/cpufreq/
H A Dcpufreq-mediatek.txt5 - clocks: A list of phandle + clock-specifier pairs for the clocks listed in clock names.
6 - clock-names: Should contain the following:
7 "cpu" - The multiplexer for clock input of CPU cluster.
8 "intermediate" - A parent of "cpu" clock which is used as "intermediate" clock
11 Please refer to Documentation/devicetree/bindings/clock/clock-bindings.txt for
13 - operating-points-v2: Please refer to Documentation/devicetree/bindings/opp/opp-v2.yaml
15 - proc-supply: Regulator for Vproc of CPU cluster.
18 - sram-supply: Regulator for Vsram of CPU cluster. When present, the cpufreq driver
23 - mediatek,cci:
30 - #cooling-cells:
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/linux/arch/arm/boot/dts/allwinner/
H A Dsun8i-a33.dtsi2 * Copyright 2014 Chen-Yu Tsai
4 * Chen-Yu Tsai <wens@csie.org>
6 * This file is dual-licensed: you can use it either under the terms
45 #include "sun8i-a23-a33.dtsi"
46 #include <dt-bindings/thermal/thermal.h>
49 cpu0_opp_table: opp-table-cpu {
50 compatible = "operating-points-v2";
51 opp-shared;
53 opp-120000000 {
54 opp-hz = /bits/ 64 <120000000>;
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/linux/arch/arm/boot/dts/ti/omap/
H A Domap34xx.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/bus/ti-sysc.h>
9 #include <dt-bindings/media/omap3-isp.h>
16 /* OMAP343x/OMAP35xx variants OPP1-6 */
17 operating-points-v2 = <&cpu0_opp_table>;
19 clock-latency = <300000>; /* From legacy driver */
20 #cooling-cells = <2>;
24 cpu0_opp_table: opp-table {
25 compatible = "operating-points-v2-ti-cpu";
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H A Dam33xx.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/bus/ti-sysc.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/pinctrl/am33xx.h>
11 #include <dt-bindings/clock/am3.h>
15 interrupt-parent = <&intc>;
16 #address-cells = <1>;
17 #size-cells = <1>;
30 d-can0 = &dcan0;
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/linux/arch/arm64/boot/dts/rockchip/
H A Drk3568.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include "rk356x-base.dtsi"
11 cpu0_opp_table: opp-table-0 {
12 compatible = "operating-points-v2";
13 opp-shared;
15 opp-408000000 {
16 opp-hz = /bits/ 64 <408000000>;
17 opp-microvolt = <850000 850000 1150000>;
18 clock-latency-ns = <40000>;
21 opp-600000000 {
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/linux/arch/arm64/boot/dts/qcom/
H A Dsa8540p.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
9 /delete-node/ &cpu0_opp_table;
10 /delete-node/ &cpu4_opp_table;
13 cpu0_opp_table: opp-table-cpu0 {
14 compatible = "operating-points-v2";
15 opp-shared;
17 opp-300000000 {
18 opp-hz = /bits/ 64 <300000000>;
19 opp-peak-kBps = <(300000 * 32)>;
21 opp-403200000 {
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H A Dmsm8996pro.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
9 /delete-node/ opp-table-cluster0;
10 /delete-node/ opp-table-cluster1;
14 * nibble of supported hw, so speed bin 0 becomes 0x10, speed bin 1
18 cluster0_opp: opp-table-cluster0 {
19 compatible = "operating-points-v2-kryo-cpu";
20 nvmem-cells = <&speedbin_efuse>;
21 opp-shared;
23 opp-307200000 {
24 opp-hz = /bits/ 64 <307200000>;
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/linux/arch/arm/boot/dts/amlogic/
H A Dmeson8.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
6 #include <dt-bindings/clock/meson8-ddr-clkc.h>
7 #include <dt-bindings/clock/meson8b-clkc.h>
8 #include <dt-bindings/gpio/meson8-gpio.h>
9 #include <dt-bindings/power/meson8-power.h>
10 #include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
11 #include <dt-bindings/reset/amlogic,meson8b-reset.h>
12 #include <dt-bindings/thermal/thermal.h>
20 #address-cells = <1>;
21 #size-cells = <0>;
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H A Dmeson8b.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 #include <dt-bindings/clock/meson8-ddr-clkc.h>
8 #include <dt-bindings/clock/meson8b-clkc.h>
9 #include <dt-bindings/gpio/meson8b-gpio.h>
10 #include <dt-bindings/power/meson8-power.h>
11 #include <dt-bindings/reset/amlogic,meson8b-reset.h>
12 #include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
13 #include <dt-bindings/thermal/thermal.h>
18 #address-cells = <1>;
19 #size-cells = <0>;
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/linux/Documentation/devicetree/bindings/power/
H A Dpower_domain.txt12 #power-domain-cells property in the PM domain provider node.
16 See power-domain.yaml.
21 - power-domains : A list of PM domain specifiers, as defined by bindings of
25 - power-domain-names : A list of power domain name strings sorted in the same
26 order as the power-domains property. Consumers drivers will use
27 power-domain-names to match power domains with power-domains
32 leaky-device@12350000 {
33 compatible = "foo,i-leak-current";
35 power-domains = <&power 0>;
36 power-domain-names = "io";
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/linux/Documentation/translations/zh_CN/power/
H A Dopp.rst1 .. SPDX-License-Identifier: GPL-2.0
2 .. include:: ../disclaimer-zh_CN.rst
4 :Original: Documentation/power/opp.rst
11 操作性能值（OPP）库
14 (C) 2009-2010 Nishanth Menon <nm@ti.com>, 德州仪器公司
18 1. 简介
25 1. 简介
28 1.1 何为操作性能值（OPP）？
29 ------------------------------
41 {300MHz，最低电压为1V}, {800MHz，最低电压为1.2V}, {1GHz，最低电压为1.3V}
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/linux/arch/arm64/boot/dts/amlogic/
H A Dmeson-g12b-a311d.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include "meson-g12b.dtsi"
10 cpu_opp_table_0: opp-table-0 {
11 compatible = "operating-points-v2";
12 opp-shared;
14 opp-1000000000 {
15 opp-hz = /bits/ 64 <1000000000>;
16 opp-microvolt = <761000>;
19 opp-1200000000 {
20 opp-hz = /bits/ 64 <1200000000>;
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H A Dmeson-g12b-s922x.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include "meson-g12b.dtsi"
10 cpu_opp_table_0: opp-table-0 {
11 compatible = "operating-points-v2";
12 opp-shared;
14 opp-1000000000 {
15 opp-hz = /bits/ 64 <1000000000>;
16 opp-microvolt = <731000>;
19 opp-1200000000 {
20 opp-hz = /bits/ 64 <1200000000>;
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/linux/arch/arm/boot/dts/intel/pxa/
H A Dpxa27x.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 #include "dt-bindings/clock/pxa-clock.h"
11 pdma: dma-controller@40000000 {
12 compatible = "marvell,pdma-1.0";
15 #dma-cells = <2>;
17 #dma-channels = <32>;
18 dma-channels = <32>;
19 #dma-requests = <75>;
20 dma-requests = <75>;
24 pxairq: interrupt-controller@40d00000 {
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/linux/Documentation/devicetree/bindings/display/msm/
H A Dqcom,sm7150-mdss.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,sm7150-mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Danila Tikhonov <danila@jiaxyga.com>
13 SM7150 MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like
16 $ref: /schemas/display/msm/mdss-common.yaml#
20 const: qcom,sm7150-mdss
24 - description: Display ahb clock from gcc
25 - description: Display hf axi clock
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