Searched full:ompic (Results 1 – 5 of 5) sorted by relevance
11 * The ompic device handles IPI communication between cores in multi-core16 * For each CPU the ompic has 2 registers. The control register for sending36 * - The ompic generates a level interrupt to the CPU PIC when a message is38 * - The ompic does not have any interrupt input lines.39 * - The ompic is wired to the same irq line on each core.55 * | ompic |<===/ | Device |<===/156 pr_err("ompic: duplicate ompic's are not supported"); in ompic_of_init()161 pr_err("ompic: reg property requires an address and size"); in ompic_of_init()166 pr_err("ompic: reg size, currently %d must be at least %d", in ompic_of_init()175 pr_err("ompic: unable to map registers"); in ompic_of_init()[all …]
4 $id: http://devicetree.org/schemas/interrupt-controller/openrisc,ompic.yaml#15 - const: openrisc,ompic40 compatible = "openrisc,ompic";
37 ompic: ompic@98000000 { label38 compatible = "openrisc,ompic";
42 select OMPIC if SMP
19307 F: drivers/irqchip/irq-ompic.c