1# SPDX-License-Identifier: GPL-2.0 2# 3# For a description of the syntax of this configuration file, 4# see Documentation/kbuild/kconfig-language.rst. 5# 6 7config OPENRISC 8 def_bool y 9 select ARCH_32BIT_OFF_T 10 select ARCH_HAS_DMA_SET_UNCACHED 11 select ARCH_HAS_DMA_CLEAR_UNCACHED 12 select ARCH_HAS_SYNC_DMA_FOR_DEVICE 13 select GENERIC_BUILTIN_DTB 14 select COMMON_CLK 15 select OF 16 select OF_EARLY_FLATTREE 17 select IRQ_DOMAIN 18 select GPIOLIB 19 select HAVE_ARCH_TRACEHOOK 20 select SPARSE_IRQ 21 select GENERIC_IRQ_CHIP 22 select GENERIC_IRQ_PROBE 23 select GENERIC_IRQ_SHOW 24 select GENERIC_PCI_IOMAP 25 select GENERIC_IOREMAP 26 select GENERIC_CPU_DEVICES 27 select HAVE_PCI 28 select HAVE_UID16 29 select HAVE_PAGE_SIZE_8KB 30 select HAVE_REGS_AND_STACK_ACCESS_API 31 select HAVE_RSEQ 32 select GENERIC_ATOMIC64 33 select GENERIC_CLOCKEVENTS_BROADCAST 34 select GENERIC_SMP_IDLE_THREAD 35 select MODULES_USE_ELF_RELA 36 select HAVE_DEBUG_STACKOVERFLOW 37 select OR1K_PIC 38 select CPU_NO_EFFICIENT_FFS if !OPENRISC_HAVE_INST_FF1 39 select ARCH_USE_QUEUED_RWLOCKS 40 select OMPIC if SMP 41 select PCI_DOMAINS_GENERIC if PCI 42 select PCI_MSI if PCI 43 select ARCH_WANT_FRAME_POINTERS 44 select GENERIC_IRQ_MULTI_HANDLER 45 select MMU_GATHER_NO_RANGE if MMU 46 select TRACE_IRQFLAGS_SUPPORT 47 48config CPU_BIG_ENDIAN 49 def_bool y 50 51config MMU 52 def_bool y 53 54config GENERIC_HWEIGHT 55 def_bool y 56 57config NO_IOPORT_MAP 58 def_bool y 59 60# For now, use generic checksum functions 61#These can be reimplemented in assembly later if so inclined 62config GENERIC_CSUM 63 def_bool y 64 65config STACKTRACE_SUPPORT 66 def_bool y 67 68config LOCKDEP_SUPPORT 69 def_bool y 70 71config FIX_EARLYCON_MEM 72 def_bool y 73 74menu "Processor type and features" 75 76choice 77 prompt "Subarchitecture" 78 default OR1K_1200 79 80config OR1K_1200 81 bool "OR1200" 82 help 83 Generic OpenRISC 1200 architecture 84 85endchoice 86 87config DCACHE_WRITETHROUGH 88 bool "Have write through data caches" 89 default n 90 help 91 Select this if your implementation features write through data caches. 92 Selecting 'N' here will allow the kernel to force flushing of data 93 caches at relevant times. Most OpenRISC implementations support write- 94 through data caches. 95 96 If unsure say N here 97 98config BUILTIN_DTB_NAME 99 string "Builtin DTB" 100 default "" 101 102menu "Class II Instructions" 103 104config OPENRISC_HAVE_INST_FF1 105 bool "Have instruction l.ff1" 106 default y 107 help 108 Select this if your implementation has the Class II instruction l.ff1 109 110config OPENRISC_HAVE_INST_FL1 111 bool "Have instruction l.fl1" 112 default y 113 help 114 Select this if your implementation has the Class II instruction l.fl1 115 116config OPENRISC_HAVE_INST_MUL 117 bool "Have instruction l.mul for hardware multiply" 118 default y 119 help 120 Select this if your implementation has a hardware multiply instruction 121 122config OPENRISC_HAVE_INST_DIV 123 bool "Have instruction l.div for hardware divide" 124 default y 125 help 126 Select this if your implementation has a hardware divide instruction 127 128config OPENRISC_HAVE_INST_CMOV 129 bool "Have instruction l.cmov for conditional move" 130 default n 131 help 132 This config enables gcc to generate l.cmov instructions when compiling 133 the kernel which in general will improve performance and reduce the 134 binary size. 135 136 Select this if your implementation has support for the Class II 137 l.cmov conistional move instruction. 138 139 Say N if you are unsure. 140 141config OPENRISC_HAVE_INST_ROR 142 bool "Have instruction l.ror for rotate right" 143 default n 144 help 145 This config enables gcc to generate l.ror instructions when compiling 146 the kernel which in general will improve performance and reduce the 147 binary size. 148 149 Select this if your implementation has support for the Class II 150 l.ror rotate right instruction. 151 152 Say N if you are unsure. 153 154config OPENRISC_HAVE_INST_RORI 155 bool "Have instruction l.rori for rotate right with immediate" 156 default n 157 help 158 This config enables gcc to generate l.rori instructions when compiling 159 the kernel which in general will improve performance and reduce the 160 binary size. 161 162 Select this if your implementation has support for the Class II 163 l.rori rotate right with immediate instruction. 164 165 Say N if you are unsure. 166 167config OPENRISC_HAVE_INST_SEXT 168 bool "Have instructions l.ext* for sign extension" 169 default n 170 help 171 This config enables gcc to generate l.ext* instructions when compiling 172 the kernel which in general will improve performance and reduce the 173 binary size. 174 175 Select this if your implementation has support for the Class II 176 l.exths, l.extbs, l.exthz and l.extbz size extend instructions. 177 178 Say N if you are unsure. 179 180endmenu 181 182config NR_CPUS 183 int "Maximum number of CPUs (2-32)" 184 range 2 32 185 depends on SMP 186 default "2" 187 188config SMP 189 bool "Symmetric Multi-Processing support" 190 help 191 This enables support for systems with more than one CPU. If you have 192 a system with only one CPU, say N. If you have a system with more 193 than one CPU, say Y. 194 195 If you don't know what to do here, say N. 196 197config FPU 198 bool "FPU support" 199 default y 200 help 201 Say N here if you want to disable all floating-point related procedures 202 in the kernel and reduce binary size. 203 204 If you don't know what to do here, say Y. 205 206source "kernel/Kconfig.hz" 207 208config OPENRISC_NO_SPR_SR_DSX 209 bool "use SPR_SR_DSX software emulation" if OR1K_1200 210 default y 211 help 212 SPR_SR_DSX bit is status register bit indicating whether 213 the last exception has happened in delay slot. 214 215 OpenRISC architecture makes it optional to have it implemented 216 in hardware and the OR1200 does not have it. 217 218 Say N here if you know that your OpenRISC processor has 219 SPR_SR_DSX bit implemented. Say Y if you are unsure. 220 221config OPENRISC_HAVE_SHADOW_GPRS 222 bool "Support for shadow gpr files" if !SMP 223 default y if SMP 224 help 225 Say Y here if your OpenRISC processor features shadowed 226 register files. They will in such case be used as a 227 scratch reg storage on exception entry. 228 229 On SMP systems, this feature is mandatory. 230 On a unicore system it's safe to say N here if you are unsure. 231 232config CMDLINE 233 string "Default kernel command string" 234 default "" 235 help 236 On some architectures there is currently no way for the boot loader 237 to pass arguments to the kernel. For these architectures, you should 238 supply some command-line options at build time by entering them 239 here. 240 241menu "Debugging options" 242 243config JUMP_UPON_UNHANDLED_EXCEPTION 244 bool "Try to die gracefully" 245 default y 246 help 247 Now this puts kernel into infinite loop after first oops. Till 248 your kernel crashes this doesn't have any influence. 249 250 Say Y if you are unsure. 251 252config OPENRISC_ESR_EXCEPTION_BUG_CHECK 253 bool "Check for possible ESR exception bug" 254 default n 255 help 256 This option enables some checks that might expose some problems 257 in kernel. 258 259 Say N if you are unsure. 260 261endmenu 262 263endmenu 264