1b2441318SGreg Kroah-Hartman# SPDX-License-Identifier: GPL-2.0 2f8c4a270SJonas Bonn# 3f8c4a270SJonas Bonn# For a description of the syntax of this configuration file, 4cd238effSMauro Carvalho Chehab# see Documentation/kbuild/kconfig-language.rst. 5f8c4a270SJonas Bonn# 6f8c4a270SJonas Bonn 7f8c4a270SJonas Bonnconfig OPENRISC 8f8c4a270SJonas Bonn def_bool y 9942fa985SYury Norov select ARCH_32BIT_OFF_T 10a4a4d11aSChristoph Hellwig select ARCH_HAS_DMA_SET_UNCACHED 11a4a4d11aSChristoph Hellwig select ARCH_HAS_DMA_CLEAR_UNCACHED 125600779eSChristoph Hellwig select ARCH_HAS_SYNC_DMA_FOR_DEVICE 13134502abSMasahiro Yamada select GENERIC_BUILTIN_DTB 147f435e42SStafford Horne select COMMON_CLK 15f8c4a270SJonas Bonn select OF 16f8c4a270SJonas Bonn select OF_EARLY_FLATTREE 17b4c4c6eeSJonas Bonn select IRQ_DOMAIN 188636f344SLinus Walleij select GPIOLIB 19f8c4a270SJonas Bonn select HAVE_ARCH_TRACEHOOK 20c0fcaf55SJonas Bonn select SPARSE_IRQ 21f8c4a270SJonas Bonn select GENERIC_IRQ_CHIP 22f8c4a270SJonas Bonn select GENERIC_IRQ_PROBE 23f8c4a270SJonas Bonn select GENERIC_IRQ_SHOW 24ded2ee36SStafford Horne select GENERIC_PCI_IOMAP 259b994429SBaoquan He select GENERIC_IOREMAP 269f13a1fdSBen Hutchings select GENERIC_CPU_DEVICES 27*8c30b001Schenmiao select HAVE_ARCH_JUMP_LABEL 28*8c30b001Schenmiao select HAVE_ARCH_JUMP_LABEL_RELATIVE 29ded2ee36SStafford Horne select HAVE_PCI 3004ea1e91SAndrew Morton select HAVE_UID16 315394f1e9SArnd Bergmann select HAVE_PAGE_SIZE_8KB 327ce8716eSMichael Jeanson select HAVE_REGS_AND_STACK_ACCESS_API 33ca46ebffSStafford Horne select HAVE_RSEQ 340662d33aSRichard Weinberger select GENERIC_ATOMIC64 358e6d08e0SStefan Kristiansson select GENERIC_CLOCKEVENTS_BROADCAST 368e6d08e0SStefan Kristiansson select GENERIC_SMP_IDLE_THREAD 37786d35d4SDavid Howells select MODULES_USE_ELF_RELA 38d1a1dc0bSDave Hansen select HAVE_DEBUG_STACKOVERFLOW 394db8e6d2SStefan Kristiansson select OR1K_PIC 40fff7fb0bSZhaoxiu Zeng select CPU_NO_EFFICIENT_FFS if !OPENRISC_HAVE_INST_FF1 41b5f82176SStafford Horne select ARCH_USE_QUEUED_RWLOCKS 429b54470aSStafford Horne select OMPIC if SMP 43ded2ee36SStafford Horne select PCI_DOMAINS_GENERIC if PCI 44ded2ee36SStafford Horne select PCI_MSI if PCI 45eecac38bSStafford Horne select ARCH_WANT_FRAME_POINTERS 46c5ca4560SPalmer Dabbelt select GENERIC_IRQ_MULTI_HANDLER 476137fed0SPeter Zijlstra select MMU_GATHER_NO_RANGE if MMU 484aae683fSMasahiro Yamada select TRACE_IRQFLAGS_SUPPORT 49f8c4a270SJonas Bonn 504c97a0c8SBabu Mogerconfig CPU_BIG_ENDIAN 514c97a0c8SBabu Moger def_bool y 524c97a0c8SBabu Moger 53f8c4a270SJonas Bonnconfig MMU 54f8c4a270SJonas Bonn def_bool y 55f8c4a270SJonas Bonn 56f8c4a270SJonas Bonnconfig GENERIC_HWEIGHT 57f8c4a270SJonas Bonn def_bool y 58f8c4a270SJonas Bonn 59ce816fa8SUwe Kleine-Königconfig NO_IOPORT_MAP 60f8c4a270SJonas Bonn def_bool y 61f8c4a270SJonas Bonn 62f8c4a270SJonas Bonn# For now, use generic checksum functions 63f8c4a270SJonas Bonn#These can be reimplemented in assembly later if so inclined 64f8c4a270SJonas Bonnconfig GENERIC_CSUM 65f8c4a270SJonas Bonn def_bool y 66f8c4a270SJonas Bonn 67eecac38bSStafford Horneconfig STACKTRACE_SUPPORT 68eecac38bSStafford Horne def_bool y 69eecac38bSStafford Horne 7078cdfb5cSStafford Horneconfig LOCKDEP_SUPPORT 7178cdfb5cSStafford Horne def_bool y 7278cdfb5cSStafford Horne 731037d186SStafford Horneconfig FIX_EARLYCON_MEM 741037d186SStafford Horne def_bool y 751037d186SStafford Horne 76f8c4a270SJonas Bonnmenu "Processor type and features" 77f8c4a270SJonas Bonn 78f8c4a270SJonas Bonnchoice 79f8c4a270SJonas Bonn prompt "Subarchitecture" 80f8c4a270SJonas Bonn default OR1K_1200 81f8c4a270SJonas Bonn 82f8c4a270SJonas Bonnconfig OR1K_1200 83f8c4a270SJonas Bonn bool "OR1200" 84f8c4a270SJonas Bonn help 85f8c4a270SJonas Bonn Generic OpenRISC 1200 architecture 86f8c4a270SJonas Bonn 87f8c4a270SJonas Bonnendchoice 88f8c4a270SJonas Bonn 894ee93d80SJan Henrik Weinstockconfig DCACHE_WRITETHROUGH 904ee93d80SJan Henrik Weinstock bool "Have write through data caches" 914ee93d80SJan Henrik Weinstock default n 924ee93d80SJan Henrik Weinstock help 934ee93d80SJan Henrik Weinstock Select this if your implementation features write through data caches. 944ee93d80SJan Henrik Weinstock Selecting 'N' here will allow the kernel to force flushing of data 954ee93d80SJan Henrik Weinstock caches at relevant times. Most OpenRISC implementations support write- 964ee93d80SJan Henrik Weinstock through data caches. 974ee93d80SJan Henrik Weinstock 984ee93d80SJan Henrik Weinstock If unsure say N here 994ee93d80SJan Henrik Weinstock 100134502abSMasahiro Yamadaconfig BUILTIN_DTB_NAME 101f8c4a270SJonas Bonn string "Builtin DTB" 102f8c4a270SJonas Bonn default "" 103f8c4a270SJonas Bonn 104f8c4a270SJonas Bonnmenu "Class II Instructions" 105f8c4a270SJonas Bonn 106f8c4a270SJonas Bonnconfig OPENRISC_HAVE_INST_FF1 107f8c4a270SJonas Bonn bool "Have instruction l.ff1" 108f8c4a270SJonas Bonn default y 109f8c4a270SJonas Bonn help 110f8c4a270SJonas Bonn Select this if your implementation has the Class II instruction l.ff1 111f8c4a270SJonas Bonn 112f8c4a270SJonas Bonnconfig OPENRISC_HAVE_INST_FL1 113f8c4a270SJonas Bonn bool "Have instruction l.fl1" 114f8c4a270SJonas Bonn default y 115f8c4a270SJonas Bonn help 116f8c4a270SJonas Bonn Select this if your implementation has the Class II instruction l.fl1 117f8c4a270SJonas Bonn 118f8c4a270SJonas Bonnconfig OPENRISC_HAVE_INST_MUL 119f8c4a270SJonas Bonn bool "Have instruction l.mul for hardware multiply" 120f8c4a270SJonas Bonn default y 121f8c4a270SJonas Bonn help 122f8c4a270SJonas Bonn Select this if your implementation has a hardware multiply instruction 123f8c4a270SJonas Bonn 124f8c4a270SJonas Bonnconfig OPENRISC_HAVE_INST_DIV 125f8c4a270SJonas Bonn bool "Have instruction l.div for hardware divide" 126f8c4a270SJonas Bonn default y 127f8c4a270SJonas Bonn help 128f8c4a270SJonas Bonn Select this if your implementation has a hardware divide instruction 12987e387acSStafford Horne 13087e387acSStafford Horneconfig OPENRISC_HAVE_INST_CMOV 13187e387acSStafford Horne bool "Have instruction l.cmov for conditional move" 13287e387acSStafford Horne default n 13387e387acSStafford Horne help 13487e387acSStafford Horne This config enables gcc to generate l.cmov instructions when compiling 13587e387acSStafford Horne the kernel which in general will improve performance and reduce the 13687e387acSStafford Horne binary size. 13787e387acSStafford Horne 13887e387acSStafford Horne Select this if your implementation has support for the Class II 13987e387acSStafford Horne l.cmov conistional move instruction. 14087e387acSStafford Horne 14187e387acSStafford Horne Say N if you are unsure. 14287e387acSStafford Horne 14387e387acSStafford Horneconfig OPENRISC_HAVE_INST_ROR 14487e387acSStafford Horne bool "Have instruction l.ror for rotate right" 14587e387acSStafford Horne default n 14687e387acSStafford Horne help 14787e387acSStafford Horne This config enables gcc to generate l.ror instructions when compiling 14887e387acSStafford Horne the kernel which in general will improve performance and reduce the 14987e387acSStafford Horne binary size. 15087e387acSStafford Horne 15187e387acSStafford Horne Select this if your implementation has support for the Class II 15287e387acSStafford Horne l.ror rotate right instruction. 15387e387acSStafford Horne 15487e387acSStafford Horne Say N if you are unsure. 15587e387acSStafford Horne 15687e387acSStafford Horneconfig OPENRISC_HAVE_INST_RORI 15787e387acSStafford Horne bool "Have instruction l.rori for rotate right with immediate" 15887e387acSStafford Horne default n 15987e387acSStafford Horne help 16087e387acSStafford Horne This config enables gcc to generate l.rori instructions when compiling 16187e387acSStafford Horne the kernel which in general will improve performance and reduce the 16287e387acSStafford Horne binary size. 16387e387acSStafford Horne 16487e387acSStafford Horne Select this if your implementation has support for the Class II 16587e387acSStafford Horne l.rori rotate right with immediate instruction. 16687e387acSStafford Horne 16787e387acSStafford Horne Say N if you are unsure. 16887e387acSStafford Horne 16987e387acSStafford Horneconfig OPENRISC_HAVE_INST_SEXT 17087e387acSStafford Horne bool "Have instructions l.ext* for sign extension" 17187e387acSStafford Horne default n 17287e387acSStafford Horne help 17387e387acSStafford Horne This config enables gcc to generate l.ext* instructions when compiling 17487e387acSStafford Horne the kernel which in general will improve performance and reduce the 17587e387acSStafford Horne binary size. 17687e387acSStafford Horne 17787e387acSStafford Horne Select this if your implementation has support for the Class II 17887e387acSStafford Horne l.exths, l.extbs, l.exthz and l.extbz size extend instructions. 17987e387acSStafford Horne 18087e387acSStafford Horne Say N if you are unsure. 18187e387acSStafford Horne 182f8c4a270SJonas Bonnendmenu 183f8c4a270SJonas Bonn 18434bbdcdcSStafford Horneconfig NR_CPUS 1858e6d08e0SStefan Kristiansson int "Maximum number of CPUs (2-32)" 1868e6d08e0SStefan Kristiansson range 2 32 1878e6d08e0SStefan Kristiansson depends on SMP 1888e6d08e0SStefan Kristiansson default "2" 1898e6d08e0SStefan Kristiansson 1908e6d08e0SStefan Kristianssonconfig SMP 1918e6d08e0SStefan Kristiansson bool "Symmetric Multi-Processing support" 1928e6d08e0SStefan Kristiansson help 1938e6d08e0SStefan Kristiansson This enables support for systems with more than one CPU. If you have 1948e6d08e0SStefan Kristiansson a system with only one CPU, say N. If you have a system with more 1958e6d08e0SStefan Kristiansson than one CPU, say Y. 1968e6d08e0SStefan Kristiansson 1978e6d08e0SStefan Kristiansson If you don't know what to do here, say N. 198f8c4a270SJonas Bonn 1991f33446dSStafford Horneconfig FPU 2001f33446dSStafford Horne bool "FPU support" 2011f33446dSStafford Horne default y 2021f33446dSStafford Horne help 2031f33446dSStafford Horne Say N here if you want to disable all floating-point related procedures 2041f33446dSStafford Horne in the kernel and reduce binary size. 2051f33446dSStafford Horne 2061f33446dSStafford Horne If you don't know what to do here, say Y. 2071f33446dSStafford Horne 2088636a1f9SMasahiro Yamadasource "kernel/Kconfig.hz" 209f8c4a270SJonas Bonn 210f8c4a270SJonas Bonnconfig OPENRISC_NO_SPR_SR_DSX 211f8c4a270SJonas Bonn bool "use SPR_SR_DSX software emulation" if OR1K_1200 212f8c4a270SJonas Bonn default y 213f8c4a270SJonas Bonn help 214f8c4a270SJonas Bonn SPR_SR_DSX bit is status register bit indicating whether 215f8c4a270SJonas Bonn the last exception has happened in delay slot. 216f8c4a270SJonas Bonn 217f8c4a270SJonas Bonn OpenRISC architecture makes it optional to have it implemented 218f8c4a270SJonas Bonn in hardware and the OR1200 does not have it. 219f8c4a270SJonas Bonn 220f8c4a270SJonas Bonn Say N here if you know that your OpenRISC processor has 221f8c4a270SJonas Bonn SPR_SR_DSX bit implemented. Say Y if you are unsure. 222f8c4a270SJonas Bonn 22391993c8cSStefan Kristianssonconfig OPENRISC_HAVE_SHADOW_GPRS 22491993c8cSStefan Kristiansson bool "Support for shadow gpr files" if !SMP 22591993c8cSStefan Kristiansson default y if SMP 22691993c8cSStefan Kristiansson help 22791993c8cSStefan Kristiansson Say Y here if your OpenRISC processor features shadowed 22891993c8cSStefan Kristiansson register files. They will in such case be used as a 22991993c8cSStefan Kristiansson scratch reg storage on exception entry. 23091993c8cSStefan Kristiansson 23191993c8cSStefan Kristiansson On SMP systems, this feature is mandatory. 23291993c8cSStefan Kristiansson On a unicore system it's safe to say N here if you are unsure. 23391993c8cSStefan Kristiansson 234f8c4a270SJonas Bonnconfig CMDLINE 235f8c4a270SJonas Bonn string "Default kernel command string" 236f8c4a270SJonas Bonn default "" 237f8c4a270SJonas Bonn help 238f8c4a270SJonas Bonn On some architectures there is currently no way for the boot loader 239f8c4a270SJonas Bonn to pass arguments to the kernel. For these architectures, you should 240f8c4a270SJonas Bonn supply some command-line options at build time by entering them 241f8c4a270SJonas Bonn here. 242f8c4a270SJonas Bonn 243f8c4a270SJonas Bonnmenu "Debugging options" 244f8c4a270SJonas Bonn 245f8c4a270SJonas Bonnconfig JUMP_UPON_UNHANDLED_EXCEPTION 246f8c4a270SJonas Bonn bool "Try to die gracefully" 247f8c4a270SJonas Bonn default y 248f8c4a270SJonas Bonn help 249f8c4a270SJonas Bonn Now this puts kernel into infinite loop after first oops. Till 250f8c4a270SJonas Bonn your kernel crashes this doesn't have any influence. 251f8c4a270SJonas Bonn 252f8c4a270SJonas Bonn Say Y if you are unsure. 253f8c4a270SJonas Bonn 254f8c4a270SJonas Bonnconfig OPENRISC_ESR_EXCEPTION_BUG_CHECK 255f8c4a270SJonas Bonn bool "Check for possible ESR exception bug" 256f8c4a270SJonas Bonn default n 257f8c4a270SJonas Bonn help 258f8c4a270SJonas Bonn This option enables some checks that might expose some problems 259f8c4a270SJonas Bonn in kernel. 260f8c4a270SJonas Bonn 261f8c4a270SJonas Bonn Say N if you are unsure. 262f8c4a270SJonas Bonn 263f8c4a270SJonas Bonnendmenu 264f8c4a270SJonas Bonn 265f8c4a270SJonas Bonnendmenu 266