| /linux/Documentation/devicetree/bindings/gpio/ |
| H A D | nuvoton,sgpio.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jim LIU <JJLIU0@nuvoton.com>
13 This SGPIO controller is for NUVOTON NPCM7xx and NPCM8xx SoC and detailed
14 information is in the NPCM7XX/8XX SERIAL I/O EXPANSION INTERFACE section.
15 Nuvoton NPCM7xx SGPIO module is combines a serial to parallel IC (HC595)
17 Clock is a division of the APB3 clock.
19 NPCM7xx/NPCM8xx have two sgpio modules. Each module can support up
22 - Support interrupt option for each input port and various interrupt
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| /linux/Documentation/devicetree/bindings/timer/ |
| H A D | nuvoton,npcm7xx-timer.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/nuvoton,npcm7xx-timer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Nuvoton NPCM7xx timer
10 - Jonathan Neuschäfer <j.neuschaefer@gmx.net>
11 - Tomer Maimon <tmaimon77@gmail.com>
16 - nuvoton,wpcm450-timer # for Hermon WPCM450
17 - nuvoton,npcm750-timer # for Poleg NPCM750
18 - nuvoton,npcm845-timer # for Arbel NPCM845
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| /linux/Documentation/devicetree/bindings/i2c/ |
| H A D | nuvoton,npcm7xx-i2c.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/i2c/nuvoton,npcm7xx-i2c.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: nuvoton NPCM7XX I2C Controller
15 - Tali Perry <tali.perry1@gmail.com>
20 - nuvoton,npcm750-i2c
21 - nuvoton,npcm845-i2c
31 description: Reference clock for the I2C bus
33 clock-frequency:
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| /linux/Documentation/devicetree/bindings/reset/ |
| H A D | nuvoton,npcm750-reset.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/reset/nuvoton,npcm750-reset.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tomer Maimon <tmaimon77@gmail.com>
15 - nuvoton,npcm750-reset # Poleg NPCM7XX SoC
16 - nuvoton,npcm845-reset # Arbel NPCM8XX SoC
21 '#reset-cells':
24 '#clock-cells':
29 - description: specify external 25MHz reference clock.
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| /linux/Documentation/devicetree/bindings/iio/adc/ |
| H A D | nuvoton,npcm750-adc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iio/adc/nuvoton,npcm750-adc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tomer Maimon <tmaimon77@gmail.com>
13 The NPCM7XX ADC is a 10-bit converter and NPCM8XX ADC is a 12-bit converter,
19 - nuvoton,npcm750-adc
20 - nuvoton,npcm845-adc
36 vref-supply:
39 "#io-channel-cells":
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| /linux/Documentation/devicetree/bindings/spi/ |
| H A D | nuvoton,npcm-pspi.txt | 3 Nuvoton NPCM7xx SOC support two PSPI channels.
6 - compatible : "nuvoton,npcm750-pspi" for Poleg NPCM7XX.
7 "nuvoton,npcm845-pspi" for Arbel NPCM8XX.
8 - #address-cells : should be 1. see spi-bus.txt
9 - #size-cells : should be 0. see spi-bus.txt
10 - specifies physical base address and size of the register.
11 - interrupts : contain PSPI interrupt.
12 - clocks : phandle of PSPI reference clock.
13 - clock-names: Should be "clk_apb5".
14 - pinctrl-names : a pinctrl state named "default" must be defined.
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| H A D | nuvoton,npcm-fiu.txt | 5 The NPCM7XX supports three FIU modules,
14 - compatible : "nuvoton,npcm750-fiu" for Poleg NPCM7XX BMC
15 "nuvoton,npcm845-fiu" for Arbel NPCM8XX BMC
16 - #address-cells : should be 1.
17 - #size-cells : should be 0.
18 - reg : the first contains the register location and length,
20 - reg-names: Should contain the reg names "control" and "memory"
21 - clocks : phandle of FIU reference clock.
24 - pinctrl-names : a pinctrl state named "default" must be defined.
25 - pinctrl-0 : phandle referencing pin configuration of the device.
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| /linux/drivers/clocksource/ |
| H A D | timer-npcm7xx.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2014-2018 Nuvoton Technologies tomer.maimon@nuvoton.com
19 #include "timer-of.h"
129 evt->event_handler(evt); in npcm7xx_timer0_interrupt()
138 .name = "npcm7xx-timer0",
184 "npcm7xx-timer1", timer_of_rate(&npcm7xx_to), in npcm7xx_clocksource_init()
198 /* Clock input is divided by PRESCALE + 1 before it is fed */ in npcm7xx_timer_init()
203 /* Enable the clock for timer1, if it exists */ in npcm7xx_timer_init()
209 pr_warn("%pOF: Failed to get clock for timer1: %pe", np, clk); in npcm7xx_timer_init()
215 pr_info("Enabling NPCM7xx clocksource timer base: %px, IRQ: %d ", in npcm7xx_timer_init()
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| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
2 menu "Clock Source drivers"
60 bool "OMAP dual-mode timer driver" if ARCH_K3 || COMPILE_TEST
64 Enables the support for the TI dual-mode timer driver.
193 bool "NPCM7xx timer driver" if COMPILE_TEST
198 Enable 24-bit TIMER0 and TIMER1 counters in the NPCM7xx architecture,
221 32-bit free running decrementing counters.
256 bool "Integrator-AP timer driver" if COMPILE_TEST
259 Enables support for the Integrator-AP timer.
284 available on many OMAP-like platforms.
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| /linux/include/dt-bindings/clock/ |
| H A D | nuvoton,npcm7xx-clock.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Nuvoton NPCM7xx Clock Generator binding
4 * clock binding number for all clocks supported by nuvoton,npcm7xx-clk
|
| /linux/drivers/clk/ |
| H A D | clk-npcm7xx.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Nuvoton NPCM7xx Clock Generator
11 #include <linux/clk-provider.h>
20 #include <dt-bindings/clock/nuvoton,npcm7xx-clock.h>
51 val = readl_relaxed(pll->pllcon); in npcm7xx_clk_pll_recalc_rate()
79 return ERR_PTR(-ENOMEM); in npcm7xx_clk_register_pll()
89 pll->pllcon = pllcon; in npcm7xx_clk_register_pll()
90 pll->hw.init = &init; in npcm7xx_clk_register_pll()
92 hw = &pll->hw; in npcm7xx_clk_register_pll()
141 * If this clock is exported via DT, set onecell_idx to constant
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| /linux/Documentation/devicetree/bindings/hwmon/ |
| H A D | npcm750-pwm-fan.txt | 3 The Nuvoton BMC NPCM7XX supports 8 Pulse-width modulation (PWM)
6 The Nuvoton BMC NPCM8XX supports 12 Pulse-width modulation (PWM)
9 Required properties for pwm-fan node
10 - #address-cells : should be 1.
11 - #size-cells : should be 0.
12 - compatible : "nuvoton,npcm750-pwm-fan" for Poleg NPCM7XX.
13 : "nuvoton,npcm845-pwm-fan" for Arbel NPCM8XX.
14 - reg : specifies physical base address and size of the registers.
15 - reg-names : must contain:
18 - clocks : phandle of reference clocks.
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| /linux/Documentation/devicetree/bindings/watchdog/ |
| H A D | nuvoton,npcm-wdt.txt | 3 Nuvoton NPCM timer module provides five 24-bit timer counters, and a watchdog.
4 The watchdog supports a pre-timeout interrupt that fires 10ms before the
8 - compatible : "nuvoton,npcm750-wdt" for NPCM750 (Poleg), or
9 "nuvoton,wpcm450-wdt" for WPCM450 (Hermon), or
10 "nuvoton,npcm845-wdt" for NPCM845 (Arbel).
11 - reg : Offset and length of the register set for the device.
12 - interrupts : Contain the timer interrupt with flags for
16 - clocks : phandle of timer reference clock.
17 - clock-frequency : The frequency in Hz of the clock that drives the NPCM7xx
21 - timeout-sec : Contains the watchdog timeout in seconds
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| /linux/drivers/hwmon/ |
| H A D | npcm750-pwm-fan.c | 1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2014-2018 Nuvoton Technology corporation.
7 #include <linux/hwmon-sysfs.h>
18 /* NPCM7XX PWM registers */
79 /* NPCM7XX FAN Tacho registers */
147 * Get Fan Tach Timeout (base on clock 214843.75Hz, 1 cnt = 4.654us)
150 * 320RPM/pulse 2, ...-- 10.6Hz)
154 #define NPCM7XX_FAN_TCPA (NPCM7XX_FAN_TCNT - NPCM7XX_FAN_TIMEOUT)
155 #define NPCM7XX_FAN_TCPB (NPCM7XX_FAN_TCNT - NPCM7XX_FAN_TIMEOUT)
224 mutex_lock(&data->pwm_lock[module]); in npcm7xx_pwm_config_set()
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| /linux/Documentation/devicetree/bindings/peci/ |
| H A D | nuvoton,npcm-peci.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/peci/nuvoton,npcm-peci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tomer Maimon <tmaimon77@gmail.com>
13 - $ref: peci-controller.yaml#
18 - nuvoton,npcm750-peci
19 - nuvoton,npcm845-peci
29 Clock source for PECI controller. Should reference the APB clock.
32 cmd-timeout-ms:
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| /linux/arch/arm/boot/dts/nuvoton/ |
| H A D | nuvoton-npcm730.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
4 #include "nuvoton-common-npcm7xx.dtsi"
7 #address-cells = <1>;
8 #size-cells = <1>;
9 interrupt-parent = <&gic>;
12 #address-cells = <1>;
13 #size-cells = <0>;
14 enable-method = "nuvoton,npcm750-smp";
18 compatible = "arm,cortex-a9";
20 clock-names = "clk_cpu";
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| H A D | nuvoton-npcm750.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
5 #include "nuvoton-common-npcm7xx.dtsi"
8 #address-cells = <1>;
9 #size-cells = <1>;
10 interrupt-parent = <&gic>;
13 #address-cells = <1>;
14 #size-cells = <0>;
15 enable-method = "nuvoton,npcm750-smp";
19 compatible = "arm,cortex-a9";
21 clock-names = "clk_cpu";
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| H A D | nuvoton-common-npcm7xx.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/clock/nuvoton,npcm7xx-clock.h>
7 #include <dt-bindings/reset/nuvoton,npcm7xx-reset.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
12 interrupt-parent = <&gic>;
14 /* external reference clock */
16 compatible = "fixed-clock";
17 #clock-cells = <0>;
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| /linux/drivers/reset/ |
| H A D | reset-npcm.c | 1 // SPDX-License-Identifier: GPL-2.0
13 #include <linux/reset-controller.h>
20 #include <soc/nuvoton/clock-npcm8xx.h>
22 /* NPCM7xx GCR registers */
40 /* NPCM7xx Reset registers */
109 writel(NPCM_SWRST << rc->sw_reset_number, rc->base + NPCM_SWRSTR); in npcm_rc_restart()
126 spin_lock_irqsave(&rc->lock, flags); in npcm_rc_setclear_reset()
127 stat = readl(rc->base + ctrl_offset); in npcm_rc_setclear_reset()
129 writel(stat | rst_bit, rc->base + ctrl_offset); in npcm_rc_setclear_reset()
131 writel(stat & ~rst_bit, rc->base + ctrl_offset); in npcm_rc_setclear_reset()
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| /linux/drivers/pinctrl/nuvoton/ |
| H A D | pinctrl-npcm7xx.c | 1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2016-2018 Nuvoton Technology corporation.
19 #include <linux/pinctrl/pinconf-generic.h>
49 #define NPCM7XX_GP_N_PU 0x1c /* Pull-up */
50 #define NPCM7XX_GP_N_PD 0x20 /* Pull-down */
108 raw_spin_lock_irqsave(&gc->bgpio_lock, flags); in npcm_gpio_set()
113 raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); in npcm_gpio_set()
122 raw_spin_lock_irqsave(&gc->bgpio_lock, flags); in npcm_gpio_clr()
127 raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); in npcm_gpio_clr()
134 seq_printf(s, "-- module %d [gpio%d - %d]\n", in npcmgpio_dbg_show()
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| /linux/drivers/i2c/busses/ |
| H A D | i2c-npcm7xx.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Nuvoton NPCM7xx I2C Controller driver
125 #define NPCM_I2CTXF_CTL 0x12 /* Tx-FIFO Control */
128 #define NPCM_I2CTXF_STS 0x1A /* Tx-FIFO Status */
129 #define NPCM_I2CRXF_STS 0x1C /* Rx-FIFO Status */
130 #define NPCM_I2CRXF_CTL 0x1E /* Rx-FIFO Control */
602 u8 i2cctl3 = ioread8(bus->reg + NPCM_I2CCTL3); in npcm_i2c_select_bank()
608 iowrite8(i2cctl3, bus->reg + NPCM_I2CCTL3); in npcm_i2c_select_bank()
613 bus->stop_ind = I2C_NO_STATUS_IND; in npcm_i2c_init_params()
614 bus->rd_size = 0; in npcm_i2c_init_params()
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| /linux/ |
| H A D | MAINTAINERS | 5 ---------------------------------------------------
21 W: *Web-page* with status/info
23 B: URI for where to file *bugs*. A web-page with detailed bug
28 patches to the given subsystem. This is either an in-tree file,
29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst
46 N: [^a-z]tegra all files whose path contains tegra
64 ----------------
83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS)
85 L: linux-scsi@vger.kernel.org
88 F: drivers/scsi/3w-*
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