1*724ba675SRob Herring// SPDX-License-Identifier: GPL-2.0 2*724ba675SRob Herring// Copyright (c) 2020 Nuvoton Technology 3*724ba675SRob Herring 4*724ba675SRob Herring#include "nuvoton-common-npcm7xx.dtsi" 5*724ba675SRob Herring 6*724ba675SRob Herring/ { 7*724ba675SRob Herring #address-cells = <1>; 8*724ba675SRob Herring #size-cells = <1>; 9*724ba675SRob Herring interrupt-parent = <&gic>; 10*724ba675SRob Herring 11*724ba675SRob Herring cpus { 12*724ba675SRob Herring #address-cells = <1>; 13*724ba675SRob Herring #size-cells = <0>; 14*724ba675SRob Herring enable-method = "nuvoton,npcm750-smp"; 15*724ba675SRob Herring 16*724ba675SRob Herring cpu@0 { 17*724ba675SRob Herring device_type = "cpu"; 18*724ba675SRob Herring compatible = "arm,cortex-a9"; 19*724ba675SRob Herring clocks = <&clk NPCM7XX_CLK_CPU>; 20*724ba675SRob Herring clock-names = "clk_cpu"; 21*724ba675SRob Herring reg = <0>; 22*724ba675SRob Herring next-level-cache = <&l2>; 23*724ba675SRob Herring }; 24*724ba675SRob Herring 25*724ba675SRob Herring cpu@1 { 26*724ba675SRob Herring device_type = "cpu"; 27*724ba675SRob Herring compatible = "arm,cortex-a9"; 28*724ba675SRob Herring clocks = <&clk NPCM7XX_CLK_CPU>; 29*724ba675SRob Herring clock-names = "clk_cpu"; 30*724ba675SRob Herring reg = <1>; 31*724ba675SRob Herring next-level-cache = <&l2>; 32*724ba675SRob Herring }; 33*724ba675SRob Herring }; 34*724ba675SRob Herring 35*724ba675SRob Herring soc { 36*724ba675SRob Herring timer@3fe600 { 37*724ba675SRob Herring compatible = "arm,cortex-a9-twd-timer"; 38*724ba675SRob Herring reg = <0x3fe600 0x20>; 39*724ba675SRob Herring interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | 40*724ba675SRob Herring IRQ_TYPE_LEVEL_HIGH)>; 41*724ba675SRob Herring clocks = <&clk NPCM7XX_CLK_AHB>; 42*724ba675SRob Herring }; 43*724ba675SRob Herring }; 44*724ba675SRob Herring}; 45