non\-cacheable (full) in projects: freebsd

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Searched +full:non +full:- +full:cacheable (Results 1 – 25 of 95) sorted by relevance

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/freebsd/lib/libpmc/pmu-events/arch/x86/amdzen1/
H A D	cache.json	5 …s transferred from IC pipe to DE instruction decoder (includes non-cacheable and cacheable fill re… 35 … instruction stream was being modified by another processor in an MP system - typically a highly u… 52 …l. IC pipe was stalled during this clock cycle (including IC to OC fetches) due to back-pressure.", 58 …be (external or LS). The number of instruction cache lines invalidated. A non-SMC event is CMC (cr… 64 …iting fill response. The number of instruction cache lines invalidated. A non-SMC event is CMC (cr… 75 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache reads (including har… 81 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache stores.", 87 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache shared reads.", 93 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Instruction cache reads.", 99 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache state change request… [all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/amdzen3/
H A D	cache.json	5 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache reads (including har… 11 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache stores.", 17 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache shared reads.", 23 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Instruction cache reads.", 29 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache state change request… 35 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). PrefetchL2Cmd.", 41 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). L2 Prefetcher. All prefetches a… 64 "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized.", 70 …riefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized non-cacheable… 76 "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Instruction cache read sized.", [all …]
H A D	memory.json	5 …"BriefDescription": "Non-forwardable conflict; used to reduce STLI's via software. All reasons. St… 6 …-to-load conflicts: A load was unable to complete due to a non-forwardable conflict with an older … 12 …"BriefDescription": "Retired lock instructions. High speculative cacheable lock speculation succee… 18 …"BriefDescription": "Retired lock instructions. Low speculative cacheable lock speculation succeed… 24 "BriefDescription": "Retired lock instructions. Non-speculative lock succeeded.", 36 … "BriefDescription": "The number of retired CLFLUSH instructions. This is a non-speculative event." 46 …"BriefDescription": "Load-op-Store Dispatch. Dispatch of a single op that performs a load from and… 84 "BriefDescription": "A non-cacheable store and the non-cacheable commit buffer is full.", 91 …esses, although these are generally rare. Each increment represents an eight-byte access, although… 258 "BriefDescription": "Total Page Table Walks on I-side.", [all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/amdzen2/
H A D	cache.json	5 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache reads (including har… 11 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache stores.", 17 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache shared reads.", 23 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Instruction cache reads.", 29 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache state change request… 35 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). PrefetchL2Cmd.", 41 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). L2 Prefetcher. All prefetches a… 64 "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized.", 70 …riefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized non-cacheable… 76 "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Instruction cache read sized.", [all …]
H A D	memory.json	5 …"BriefDescription": "Non-forwardable conflict; used to reduce STLI's via software. All reasons. St… 6 …-to-load conflicts: A load was unable to complete due to a non-forwardable conflict with an older … 12 …"BriefDescription": "Retired lock instructions. High speculative cacheable lock speculation succee… 18 …"BriefDescription": "Retired lock instructions. Low speculative cacheable lock speculation succeed… 24 "BriefDescription": "Retired lock instructions. Non-speculative lock succeeded.", 84 "BriefDescription": "A non-cacheable store and the non-cacheable commit buffer is full." 90 …esses, although these are generally rare. Each increment represents an eight-byte access, although… 197 "BriefDescription": "Total Page Table Walks on I-side.", 215 "BriefDescription": "Total Page Table Walks on D-side.", 262 … the processor core. Software PREFETCH instruction saw a match on an already-allocated miss reques…
/freebsd/sys/riscv/include/
H A D	pte.h	`1 /- 3 Copyright (c) 2015-2018 Ruslan Bukin <br@bsdpad.com> 8 * FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme. 48 #define L0_OFFSET (L0_SIZE - 1) 53 #define L1_OFFSET (L1_SIZE - 1) 58 #define L2_OFFSET (L2_SIZE - 1) 63 #define L3_OFFSET (L3_SIZE - 1) 67 #define Ln_ADDR_MASK (Ln_ENTRIES - 1) 89 * +------+-------+------------------------------------------------------------+ 91 * +------+-------+------------------------------------------------------------+ [all …]`
/freebsd/lib/libpmc/pmu-events/arch/arm64/arm/cortex-a65/
H A D	memory.json	`30 "PublicDescription": "External memory request to non-cacheable memory", 33 "BriefDescription": "External memory request to non-cacheable memory"`
/freebsd/lib/libpmc/pmu-events/arch/x86/icelakex/
H A D	cache.json	9 …opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.", 21 … due to L1D Fill Buffer (FB) unavailablability. Demand requests include cacheable/uncacheable dema… 35 … due to L1D Fill Buffer (FB) unavailablability. Demand requests include cacheable/uncacheable dema… 47 … waited due to L1D due to lack of L2 resources. Demand requests include cacheable/uncacheable dema… 59 …non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined u… 102 …"BriefDescription": "Non-modified cache lines that are silently dropped by L2 cache when triggered… 108 …y an L2 cache fill. These lines are typically in Shared or Exclusive state. A non-threaded event.", 132 …from L1D hardware prefetchers). These loads may hit or miss L2 cache. Only non rejected loads are … 216 "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that hit L2 cache.", 228 "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that miss L2 cache.", [all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/ivybridge/
H A D	uncore.json	19 "BriefDescription": "A snoop invalidates a non-modified line in some processor core.", 20 "PublicDescription": "A snoop invalidates a non-modified line in some processor core.", 31 "BriefDescription": "A snoop hits a non-modified line in some processor core.", 32 "PublicDescription": "A snoop hits a non-modified line in some processor core.", 67 …"BriefDescription": "Filter on cross-core snoops initiated by this Cbox due to external snoop requ… 68 …"PublicDescription": "Filter on cross-core snoops initiated by this Cbox due to external snoop req… 79 …"BriefDescription": "Filter on cross-core snoops initiated by this Cbox due to processor core memo… 80 …"PublicDescription": "Filter on cross-core snoops initiated by this Cbox due to processor core mem… 91 "BriefDescription": "Filter on cross-core snoops initiated by this Cbox due to LLC eviction.", 92 "PublicDescription": "Filter on cross-core snoops initiated by this Cbox due to LLC eviction.", [all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/sandybridge/
H A D	uncore.json	19 "BriefDescription": "A snoop invalidates a non-modified line in some processor core.", 20 "PublicDescription": "A snoop invalidates a non-modified line in some processor core.", 31 "BriefDescription": "A snoop hits a non-modified line in some processor core.", 32 "PublicDescription": "A snoop hits a non-modified line in some processor core.", 67 …"BriefDescription": "Filter on cross-core snoops initiated by this Cbox due to external snoop requ… 68 …"PublicDescription": "Filter on cross-core snoops initiated by this Cbox due to external snoop req… 79 …"BriefDescription": "Filter on cross-core snoops initiated by this Cbox due to processor core memo… 80 …"PublicDescription": "Filter on cross-core snoops initiated by this Cbox due to processor core mem… 91 "BriefDescription": "Filter on cross-core snoops initiated by this Cbox due to LLC eviction.", 92 "PublicDescription": "Filter on cross-core snoops initiated by this Cbox due to LLC eviction.", [all …]
/freebsd/sys/contrib/device-tree/Bindings/pmem/
H A D	pmem-region.txt	`1 Device-tree bindings for persistent memory regions 2 --------- [all...]`
/freebsd/sys/arm64/arm64/
H A D	gic_v3_reg.h	`1 /- 145 0x0 - Device-nGnRnE 146 * 0x1 - Normal Inner Non-cacheable 147 * 0x2 - Normal Inner Read-allocate, Write-through 148 * 0x3 - Normal Inner Read-allocate, Write-back 149 * 0x4 - Normal Inner Write-allocate, Write-through 150 * 0x5 - Normal Inner Write-allocate, Write-back 151 * 0x6 - Normal Inner Read-allocate, Write-allocate, Write-through 152 * 0x7 - Normal Inner Read-allocate, Write-allocate, Write-back 168 * 0x0 - Non-shareable [all …]`
/freebsd/lib/libpmc/pmu-events/arch/x86/elkhartlake/
H A D	cache.json	15 …"BriefDescription": "Counts the number of cacheable memory requests that miss in the LLC. Counts o… 22 …"PublicDescription": "Counts the number of cacheable memory requests that miss in the Last Level C… 27 …"BriefDescription": "Counts the number of cacheable memory requests that access the LLC. Counts on… 34 …"PublicDescription": "Counts the number of cacheable memory requests that access the Last Level Ca… 39 …the core is stalled due to an instruction cache or TLB miss which hit in DRAM or MMIO (Non-DRAM).", 46 …truction cache or translation lookaside buffer (TLB) access which hit in DRAM or MMIO (non-DRAM).", 75 …ber of cycles the core is stalled due to a demand load miss which hit in DRAM or MMIO (Non-DRAM).",
/freebsd/lib/libpmc/pmu-events/arch/x86/sapphirerapids/
H A D	cache.json	9 …opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.", 20 … due to L1D Fill Buffer (FB) unavailablability. Demand requests include cacheable/uncacheable dema… 33 … due to L1D Fill Buffer (FB) unavailablability. Demand requests include cacheable/uncacheable dema… 54 … waited due to L1D due to lack of L2 resources. Demand requests include cacheable/uncacheable dema… 65 …non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined u… 103 …"BriefDescription": "Non-modified cache lines that are silently dropped by L2 cache when triggered… 109 …y an L2 cache fill. These lines are typically in Shared or Exclusive state. A non-threaded event.", 125 …"BriefDescription": "Read requests with true-miss in L2 cache.[This event is alias to L2_RQSTS.MIS… 131 …ublicDescription": "Counts read requests of any type with true-miss in the L2 cache. True-miss exc… 153 …from L1D hardware prefetchers). These loads may hit or miss L2 cache. Only non rejected loads are … [all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/tremontx/
H A D	cache.json	33 … The XQ may reject transactions from the L2Q (non-cacheable requests), BBL (L2 misses) and WOB (L… 84 …"BriefDescription": "Counts the number of cacheable memory requests that miss in the LLC. Counts o… 91 …"PublicDescription": "Counts the number of cacheable memory requests that miss in the Last Level C… 96 …"BriefDescription": "Counts the number of cacheable memory requests that access the LLC. Counts on… 103 …"PublicDescription": "Counts the number of cacheable memory requests that access the Last Level Ca… 108 …talled due to an instruction cache or TLB miss which hit in the L2, LLC, DRAM or MMIO (Non-DRAM).", 118 …the core is stalled due to an instruction cache or TLB miss which hit in DRAM or MMIO (Non-DRAM).", 125 …truction cache or translation lookaside buffer (TLB) access which hit in DRAM or MMIO (non-DRAM).", 154 … the core is stalled due to a demand load miss which hit in the L2, LLC, DRAM or MMIO (Non-DRAM).", 164 …ber of cycles the core is stalled due to a demand load miss which hit in DRAM or MMIO (Non-DRAM).", [all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/tigerlake/
H A D	cache.json	9 …opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.", 20 … due to L1D Fill Buffer (FB) unavailablability. Demand requests include cacheable/uncacheable dema… 33 … due to L1D Fill Buffer (FB) unavailablability. Demand requests include cacheable/uncacheable dema… 44 … waited due to L1D due to lack of L2 resources. Demand requests include cacheable/uncacheable dema… 55 …non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined u… 94 …"BriefDescription": "Non-modified cache lines that are silently dropped by L2 cache when triggered… 100 …y an L2 cache fill. These lines are typically in Shared or Exclusive state. A non-threaded event.", 177 "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that hit L2 cache.", 188 "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that miss L2 cache.", 237 …"BriefDescription": "Core-originated cacheable requests that missed L3 (Except hardware prefetche… [all …]
/freebsd/lib/libpmc/
H A D	pmc.core.3	`50 .%B IA-32 Intel\(rg Architecture Software Developer's Manual 52 .%N Order Number 253669-027US 63 .Bl -column "PMC_CAP_INTERRUPT" "Support" 80 .Bl -tag -width indent 86 Configure the PMC to count the number of de-asserted to asserted 112 Events that require core-specificity to be specified use a 118 .Bl -tag -width indent -compact 133 .Bl -tag -width indent -compact 148 .Bl -tag -width "exclude" -compact 165 .Bl -tag -width indent -compact [all …]`
H A D	pmc.haswelluc.3	45 .Bl -tag -width "Li PMC_CLASS_UCP" 47 Fixed-function counters that count only one hardware event per counter. 59 .%B "Intel(R) 64 and IA-32 Architectures Software Developers Manual" 61 .%N "Order Number: 325462-045US" 68 Not all CPUs in this family implement fixed-function counters. 71 .Bl -column "PMC_CAP_INTERRUPT" "Support" 88 .Bl -tag -width indent 94 Configure the PMC to count the number of de-asserted to asserted 109 .Bl -tag -width indent 115 A snoop invalidates a non-modified line in some [all …]
/freebsd/lib/libpmc/pmu-events/arch/arm64/arm/cortex-a55/
H A D	pipeline.json	`21 …ion issued due to the frontend, pre-decode error.This event counts every cycle the DPU IQ is empty… 24 …ion issued due to the frontend, pre-decode error.This event counts every cycle the DPU IQ is empty… 57 …Wr stage due to a load which is waiting on data (due to missing the cache or being non-cacheable)", 60 … Wr stage due to a load which is waiting on data (due to missing the cache or being non-cacheable)"`
/freebsd/lib/libpmc/pmu-events/arch/x86/goldmont/
H A D	cache.json	22 "BriefDescription": "Cycles code-fetch stalled due to an outstanding ICache miss.", 37 …from the intra-die interconnect (IDI) fabric. The XQ may reject transactions from the L2Q (non-cac… 193 "BriefDescription": "Memory uops retired that split a cache-line (Precise event capable)", 205 "BriefDescription": "Load uops retired that split a cache-line (Precise event capable)", 217 "BriefDescription": "Stores uops retired that split a cache-line (Precise event capable)", 641 …"BriefDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss th… 649 …"PublicDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss t… 654 …"BriefDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss th… 662 …"PublicDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss t… 667 …"BriefDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss th… [all …]
/freebsd/sys/contrib/device-tree/Bindings/arm/
H A D	l2c2x0.yaml	`1 # SPDX-License-Identifier: GPL-2.0 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Rob Herring <robh@kernel.org> 16 models (Note 1). Some of the properties that are just prefixed "cache-*" are 22 cache controllers as found in e.g. Cortex-A15/A7/A57/A53. These 28 - $ref: /schemas/cache-controller.yaml# 33 - enum: 34 - arm,pl310-cache 35 - arm,l220-cache [all …]`
/freebsd/sys/contrib/device-tree/Bindings/cache/
H A D	l2c2x0.yaml	`1 # SPDX-License-Identifier: GPL-2.0 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Rob Herring <robh@kernel.org> 16 models (Note 1). Some of the properties that are just prefixed "cache-*" are 22 cache controllers as found in e.g. Cortex-A15/A7/A57/A53. These 28 - $ref: /schemas/cache-controller.yaml# 33 - enum: 34 - arm,pl310-cache 35 - arm,l220-cache [all …]`
/freebsd/lib/libpmc/pmu-events/arch/x86/icelake/
H A D	cache.json	9 …opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.", 21 … due to L1D Fill Buffer (FB) unavailablability. Demand requests include cacheable/uncacheable dema… 35 … due to L1D Fill Buffer (FB) unavailablability. Demand requests include cacheable/uncacheable dema… 47 … waited due to L1D due to lack of L2 resources. Demand requests include cacheable/uncacheable dema… 59 …non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined u… 102 …"BriefDescription": "Non-modified cache lines that are silently dropped by L2 cache when triggered… 108 …y an L2 cache fill. These lines are typically in Shared or Exclusive state. A non-threaded event.", 144 …from L1D hardware prefetchers). These loads may hit or miss L2 cache. Only non rejected loads are … 240 "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that hit L2 cache.", 252 "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that miss L2 cache.", [all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/broadwellde/
H A D	cache.json	8 …opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.", 28 …non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined u… 129 …from L1D hardware prefetchers). These loads may hit or miss L2 cache. Only non rejected loads are … 356 "BriefDescription": "Core-originated cacheable demand requests missed L3", 361 …"PublicDescription": "This event counts core-originated cacheable demand requests that miss the la… 366 "BriefDescription": "Core-originated cacheable demand requests that refer to L3", 371 …"PublicDescription": "This event counts core-originated cacheable demand requests that refer to th… 376 …ed load uops which data sources were L3 and cross-core snoop hits in on-pkg core cache. (Precise E… 384 …ts retired load uops which data sources were L3 hit and a cross-core snoop hit in the on-pkg core … 389 … "Retired load uops which data sources were HitM responses from shared L3. (Precise Event - PEBS)", [all …]
/freebsd/lib/libpmc/pmu-events/arch/arm64/arm/cortex-a53/
H A D	memory.json	`10 "BriefDescription": "Non-cacheable external memory request"`

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