Lines Matching +full:non +full:- +full:cacheable

9 …opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.",
21 … due to L1D Fill Buffer (FB) unavailablability. Demand requests include cacheable/uncacheable dema…
35 … due to L1D Fill Buffer (FB) unavailablability. Demand requests include cacheable/uncacheable dema…
47 … waited due to L1D due to lack of L2 resources. Demand requests include cacheable/uncacheable dema…
59 …non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined u…
102 …"BriefDescription": "Non-modified cache lines that are silently dropped by L2 cache when triggered…
108 …y an L2 cache fill. These lines are typically in Shared or Exclusive state. A non-threaded event.",
132 …from L1D hardware prefetchers). These loads may hit or miss L2 cache. Only non rejected loads are …
216         "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that hit L2 cache.",
228         "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that miss L2 cache.",
270 …"BriefDescription": "Core-originated cacheable requests that missed L3  (Except hardware prefetche…
276 … "Counts core-originated cacheable requests that miss the L3 cache (Longest Latency cache). Reques…
282 …"BriefDescription": "Core-originated cacheable requests that refer to L3 (Except hardware prefetch…
288 …n": "Counts core-originated cacheable requests to the L3 cache (Longest Latency cache). Requests i…
330         "PublicDescription": "Counts all retired memory instructions - loads and stores.",
383 …"PublicDescription": "Number of retired load instructions that (start a) miss in the 2nd-level TLB…
397 …"PublicDescription": "Number of retired store instructions that (start a) miss in the 2nd-level TL…
440 …tired load instructions whose data sources were L3 hit and cross-core snoop missed in on-pkg core …
448 …tired load instructions whose data sources were L3 hit and cross-core snoop missed in on-pkg core …
466 …: "Retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core c…
474 …ts retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core c…
552 …ired instructions with at least one load to uncacheable memory-type, or at least one cache-line sp…
683 …m a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.",
694 …r hit a non-modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches…
771 …m a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.",
782 …r hit a non-modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches…
815 …m a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.",
826 …r hit a non-modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches…
947 …m a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.",
958 …r hit a non-modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches…
986 …"Counts the demand and prefetch data reads. All Core Data Reads include cacheable 'Demands' and L2…
1004         "BriefDescription": "Counts cacheable and non-cacheable code reads to the core.",
1010         "PublicDescription": "Counts both cacheable and non-cacheable code reads to the core.",
1046 … of outstanding data read requests pending.  Data read requests include cacheable demand reads and…
1059 …1 outstanding data read request is pending.  Data read requests include cacheable demand reads and…
1072 …g code read requests pending.  Code Read requests include both cacheable and non-cacheable Code Re…
1097 …g code read requests pending.  Code Read requests include both cacheable and non-cacheable Code Re…