Lines Matching +full:non +full:- +full:cacheable
1 /*-
3 * Copyright (c) 2015-2018 Ruslan Bukin <br@bsdpad.com>
8 * FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme.
48 #define L0_OFFSET (L0_SIZE - 1)
53 #define L1_OFFSET (L1_SIZE - 1)
58 #define L2_OFFSET (L2_SIZE - 1)
63 #define L3_OFFSET (L3_SIZE - 1)
67 #define Ln_ADDR_MASK (Ln_ENTRIES - 1)
89 * +------+-------+------------------------------------------------------------+
91 * +------+-------+------------------------------------------------------------+
93 * | NC | 01 | Non-cacheable, idempotent, weakly-ordered (RVWMO), |
95 * | IO | 10 | Non-cacheable, non-idempotent, strongly-ordered, I/O |
96 * | -- | 11 | Reserved |
97 * +------+-------+------------------------------------------------------------+
106 * T-HEAD Custom Memory Attribute (MA) bits [63:59].
111 * bit 62: Cacheable
114 * +------+-------+------------------------------------------------------------+
116 * +------+-------+------------------------------------------------------------+
117 * | NC | 00110 | Weakly-ordered, non-cacheable, bufferable, shareable, |
118 * | | | non-trustable |
119 * | PMA | 01110 | Weakly-ordered, cacheable, bufferable, shareable, |
120 * | | | non-trustable |
121 * | IO | 10010 | Strongly-ordered, non-cacheable, non-bufferable, |
122 * | | | shareable, non-trustable |
123 * +------+-------+------------------------------------------------------------+
131 /* Bits 63 - 54 are reserved for future use. */