1[ 2 { 3 "Unit": "CBO", 4 "EventCode": "0x22", 5 "UMask": "0x01", 6 "EventName": "UNC_CBO_XSNP_RESPONSE.MISS", 7 "BriefDescription": "A snoop misses in some processor core.", 8 "PublicDescription": "A snoop misses in some processor core.", 9 "Counter": "0,1", 10 "CounterMask": "0", 11 "Invert": "0", 12 "EdgeDetect": "0" 13 }, 14 { 15 "Unit": "CBO", 16 "EventCode": "0x22", 17 "UMask": "0x02", 18 "EventName": "UNC_CBO_XSNP_RESPONSE.INVAL", 19 "BriefDescription": "A snoop invalidates a non-modified line in some processor core.", 20 "PublicDescription": "A snoop invalidates a non-modified line in some processor core.", 21 "Counter": "0,1", 22 "CounterMask": "0", 23 "Invert": "0", 24 "EdgeDetect": "0" 25 }, 26 { 27 "Unit": "CBO", 28 "EventCode": "0x22", 29 "UMask": "0x04", 30 "EventName": "UNC_CBO_XSNP_RESPONSE.HIT", 31 "BriefDescription": "A snoop hits a non-modified line in some processor core.", 32 "PublicDescription": "A snoop hits a non-modified line in some processor core.", 33 "Counter": "0,1", 34 "CounterMask": "0", 35 "Invert": "0", 36 "EdgeDetect": "0" 37 }, 38 { 39 "Unit": "CBO", 40 "EventCode": "0x22", 41 "UMask": "0x08", 42 "EventName": "UNC_CBO_XSNP_RESPONSE.HITM", 43 "BriefDescription": "A snoop hits a modified line in some processor core.", 44 "PublicDescription": "A snoop hits a modified line in some processor core.", 45 "Counter": "0,1", 46 "CounterMask": "0", 47 "Invert": "0", 48 "EdgeDetect": "0" 49 }, 50 { 51 "Unit": "CBO", 52 "EventCode": "0x22", 53 "UMask": "0x10", 54 "EventName": "UNC_CBO_XSNP_RESPONSE.INVAL_M", 55 "BriefDescription": "A snoop invalidates a modified line in some processor core.", 56 "PublicDescription": "A snoop invalidates a modified line in some processor core.", 57 "Counter": "0,1", 58 "CounterMask": "0", 59 "Invert": "0", 60 "EdgeDetect": "0" 61 }, 62 { 63 "Unit": "CBO", 64 "EventCode": "0x22", 65 "UMask": "0x20", 66 "EventName": "UNC_CBO_XSNP_RESPONSE.EXTERNAL_FILTER", 67 "BriefDescription": "Filter on cross-core snoops initiated by this Cbox due to external snoop request.", 68 "PublicDescription": "Filter on cross-core snoops initiated by this Cbox due to external snoop request.", 69 "Counter": "0,1", 70 "CounterMask": "0", 71 "Invert": "0", 72 "EdgeDetect": "0" 73 }, 74 { 75 "Unit": "CBO", 76 "EventCode": "0x22", 77 "UMask": "0x40", 78 "EventName": "UNC_CBO_XSNP_RESPONSE.XCORE_FILTER", 79 "BriefDescription": "Filter on cross-core snoops initiated by this Cbox due to processor core memory request.", 80 "PublicDescription": "Filter on cross-core snoops initiated by this Cbox due to processor core memory request.", 81 "Counter": "0,1", 82 "CounterMask": "0", 83 "Invert": "0", 84 "EdgeDetect": "0" 85 }, 86 { 87 "Unit": "CBO", 88 "EventCode": "0x22", 89 "UMask": "0x80", 90 "EventName": "UNC_CBO_XSNP_RESPONSE.EVICTION_FILTER", 91 "BriefDescription": "Filter on cross-core snoops initiated by this Cbox due to LLC eviction.", 92 "PublicDescription": "Filter on cross-core snoops initiated by this Cbox due to LLC eviction.", 93 "Counter": "0,1", 94 "CounterMask": "0", 95 "Invert": "0", 96 "EdgeDetect": "0" 97 }, 98 { 99 "Unit": "CBO", 100 "EventCode": "0x34", 101 "UMask": "0x01", 102 "EventName": "UNC_CBO_CACHE_LOOKUP.M", 103 "BriefDescription": "LLC lookup request that access cache and found line in M-state.", 104 "PublicDescription": "LLC lookup request that access cache and found line in M-state.", 105 "Counter": "0,1", 106 "CounterMask": "0", 107 "Invert": "0", 108 "EdgeDetect": "0" 109 }, 110 { 111 "Unit": "CBO", 112 "EventCode": "0x34", 113 "UMask": "0x02", 114 "EventName": "UNC_CBO_CACHE_LOOKUP.E", 115 "BriefDescription": "LLC lookup request that access cache and found line in E-state.", 116 "PublicDescription": "LLC lookup request that access cache and found line in E-state.", 117 "Counter": "0,1", 118 "CounterMask": "0", 119 "Invert": "0", 120 "EdgeDetect": "0" 121 }, 122 { 123 "Unit": "CBO", 124 "EventCode": "0x34", 125 "UMask": "0x04", 126 "EventName": "UNC_CBO_CACHE_LOOKUP.S", 127 "BriefDescription": "LLC lookup request that access cache and found line in S-state.", 128 "PublicDescription": "LLC lookup request that access cache and found line in S-state.", 129 "Counter": "0,1", 130 "CounterMask": "0", 131 "Invert": "0", 132 "EdgeDetect": "0" 133 }, 134 { 135 "Unit": "CBO", 136 "EventCode": "0x34", 137 "UMask": "0x08", 138 "EventName": "UNC_CBO_CACHE_LOOKUP.I", 139 "BriefDescription": "LLC lookup request that access cache and found line in I-state.", 140 "PublicDescription": "LLC lookup request that access cache and found line in I-state.", 141 "Counter": "0,1", 142 "CounterMask": "0", 143 "Invert": "0", 144 "EdgeDetect": "0" 145 }, 146 { 147 "Unit": "CBO", 148 "EventCode": "0x34", 149 "UMask": "0x10", 150 "EventName": "UNC_CBO_CACHE_LOOKUP.READ_FILTER", 151 "BriefDescription": "Filter on processor core initiated cacheable read requests.", 152 "PublicDescription": "Filter on processor core initiated cacheable read requests.", 153 "Counter": "0,1", 154 "CounterMask": "0", 155 "Invert": "0", 156 "EdgeDetect": "0" 157 }, 158 { 159 "Unit": "CBO", 160 "EventCode": "0x34", 161 "UMask": "0x20", 162 "EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_FILTER", 163 "BriefDescription": "Filter on processor core initiated cacheable write requests.", 164 "PublicDescription": "Filter on processor core initiated cacheable write requests.", 165 "Counter": "0,1", 166 "CounterMask": "0", 167 "Invert": "0", 168 "EdgeDetect": "0" 169 }, 170 { 171 "Unit": "CBO", 172 "EventCode": "0x34", 173 "UMask": "0x40", 174 "EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_FILTER", 175 "BriefDescription": "Filter on external snoop requests.", 176 "PublicDescription": "Filter on external snoop requests.", 177 "Counter": "0,1", 178 "CounterMask": "0", 179 "Invert": "0", 180 "EdgeDetect": "0" 181 }, 182 { 183 "Unit": "CBO", 184 "EventCode": "0x34", 185 "UMask": "0x80", 186 "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_REQUEST_FILTER", 187 "BriefDescription": "Filter on any IRQ or IPQ initiated requests including uncacheable, non-coherent requests.", 188 "PublicDescription": "Filter on any IRQ or IPQ initiated requests including uncacheable, non-coherent requests.", 189 "Counter": "0,1", 190 "CounterMask": "0", 191 "Invert": "0", 192 "EdgeDetect": "0" 193 }, 194 { 195 "Unit": "ARB", 196 "EventCode": "0x80", 197 "UMask": "0x01", 198 "EventName": "UNC_ARB_TRK_OCCUPANCY.ALL", 199 "BriefDescription": "Counts cycles weighted by the number of requests waiting for data returning from the memory controller. Accounts for coherent and non-coherent requests initiated by IA cores, processor graphic units, or LLC.", 200 "PublicDescription": "Counts cycles weighted by the number of requests waiting for data returning from the memory controller. Accounts for coherent and non-coherent requests initiated by IA cores, processor graphic units, or LLC.", 201 "Counter": "0", 202 "CounterMask": "0", 203 "Invert": "0", 204 "EdgeDetect": "0" 205 }, 206 { 207 "Unit": "ARB", 208 "EventCode": "0x81", 209 "UMask": "0x01", 210 "EventName": "UNC_ARB_TRK_REQUESTS.ALL", 211 "BriefDescription": "Counts the number of coherent and in-coherent requests initiated by IA cores, processor graphic units, or LLC.", 212 "PublicDescription": "Counts the number of coherent and in-coherent requests initiated by IA cores, processor graphic units, or LLC.", 213 "Counter": "0,1", 214 "CounterMask": "0", 215 "Invert": "0", 216 "EdgeDetect": "0" 217 }, 218 { 219 "Unit": "ARB", 220 "EventCode": "0x81", 221 "UMask": "0x20", 222 "EventName": "UNC_ARB_TRK_REQUESTS.WRITES", 223 "BriefDescription": "Counts the number of allocated write entries, include full, partial, and LLC evictions.", 224 "PublicDescription": "Counts the number of allocated write entries, include full, partial, and LLC evictions.", 225 "Counter": "0,1", 226 "CounterMask": "0", 227 "Invert": "0", 228 "EdgeDetect": "0" 229 }, 230 { 231 "Unit": "ARB", 232 "EventCode": "0x81", 233 "UMask": "0x80", 234 "EventName": "UNC_ARB_TRK_REQUESTS.EVICTIONS", 235 "BriefDescription": "Counts the number of LLC evictions allocated.", 236 "PublicDescription": "Counts the number of LLC evictions allocated.", 237 "Counter": "0,1", 238 "CounterMask": "0", 239 "Invert": "0", 240 "EdgeDetect": "0" 241 }, 242 { 243 "Unit": "ARB", 244 "EventCode": "0x83", 245 "UMask": "0x01", 246 "EventName": "UNC_ARB_COH_TRK_OCCUPANCY.ALL", 247 "BriefDescription": "Cycles weighted by number of requests pending in Coherency Tracker.", 248 "PublicDescription": "Cycles weighted by number of requests pending in Coherency Tracker.", 249 "Counter": "0", 250 "CounterMask": "0", 251 "Invert": "0", 252 "EdgeDetect": "0" 253 }, 254 { 255 "Unit": "ARB", 256 "EventCode": "0x84", 257 "UMask": "0x01", 258 "EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL", 259 "BriefDescription": "Number of requests allocated in Coherency Tracker.", 260 "PublicDescription": "Number of requests allocated in Coherency Tracker.", 261 "Counter": "0,1", 262 "CounterMask": "0", 263 "Invert": "0", 264 "EdgeDetect": "0" 265 }, 266 { 267 "Unit": "ARB", 268 "EventCode": "0x80", 269 "UMask": "0x01", 270 "EventName": "UNC_ARB_TRK_OCCUPANCY.CYCLES_WITH_ANY_REQUEST", 271 "BriefDescription": "Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.", 272 "PublicDescription": "Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.", 273 "Counter": "0,1", 274 "CounterMask": "1", 275 "Invert": "0", 276 "EdgeDetect": "0" 277 }, 278 { 279 "Unit": "ARB", 280 "EventCode": "0x80", 281 "UMask": "0x01", 282 "EventName": "UNC_ARB_TRK_OCCUPANCY.CYCLES_OVER_HALF_FULL", 283 "BriefDescription": "Cycles with at least half of the requests outstanding are waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.", 284 "PublicDescription": "Cycles with at least half of the requests outstanding are waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.", 285 "Counter": "0,1", 286 "CounterMask": "10", 287 "Invert": "0", 288 "EdgeDetect": "0" 289 }, 290 { 291 "Unit": "ARB", 292 "EventCode": "0x0", 293 "UMask": "0x01", 294 "EventName": "UNC_CLOCK.SOCKET", 295 "BriefDescription": "This 48-bit fixed counter counts the UCLK cycles.", 296 "PublicDescription": "This 48-bit fixed counter counts the UCLK cycles.", 297 "Counter": "Fixed", 298 "CounterMask": "0", 299 "Invert": "0", 300 "EdgeDetect": "0" 301 }, 302 { 303 "Unit": "CBO", 304 "EventCode": "0x34", 305 "UMask": "0x06", 306 "EventName": "UNC_CBO_CACHE_LOOKUP.ES", 307 "BriefDescription": "LLC lookup request that access cache and found line in E-state or S-state.", 308 "PublicDescription": "LLC lookup request that access cache and found line in E-state or S-state.", 309 "Counter": "0,1", 310 "CounterMask": "0", 311 "Invert": "0", 312 "EdgeDetect": "0" 313 } 314]