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/linux/arch/arm/boot/dts/ti/omap/
H A Domap3-beagle-ab4.dts1 // SPDX-License-Identifier: GPL-2.0-only
2 /dts-v1/;
4 #include "omap3-beagle.dts"
8 compatible = "ti,omap3-beagle-ab4", "ti,omap3-beagle", "ti,omap3430", "ti,omap3";
23 /delete-property/ti,no-reset-on-init;
24 /delete-property/ti,no-idle;
26 /delete-property/ti,timer-alwon;
30 /* Preferred always-on timer for clocksource */
32 ti,no-reset-on-init;
33 ti,no-idle;
[all …]
H A Domap3-sniper.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2015-2016 Paul Kocialkowski <contact@paulk.fr>
5 /dts-v1/;
8 #include <dt-bindings/input/input.h>
12 compatible = "lg,omap3-sniper", "ti,omap3630", "ti,omap3";
16 cpu0-supply = <&vcc>;
27 pinctrl-names = "default";
29 uart3_pins: uart3-pins {
30 pinctrl-single,pins = <
36 dp3t_sel_pins: dp3t-sel-pins {
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H A Dam3517.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
11 /delete-node/ &aes1_target;
12 /delete-node/ &aes2_target;
23 /* Based on OMAP3630 variants OPP50 and OPP100 */
24 operating-points-v2 = <&cpu0_opp_table>;
26 clock-latency = <300000>; /* From legacy driver */
30 cpu0_opp_table: opp-table {
31 compatible = "operating-points-v2-ti-cpu";
38 opp-50-300000000 {
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/linux/arch/arm/mach-omap2/
H A Dprm_common.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * OMAP2+ common Power & Reset Management (PRM) IP block functions
6 * Tero Kristo <t-kristo@ti.com>
10 * underlying registers are located in the PRM on OMAP3/4.
17 #include <linux/init.h>
24 #include <linux/clk-provider.h>
44 * omap_prcm_register_chain_handler() could allocate this based on the
59 * is currently running on. Defined and passed by initialization code
76 * prm_ll_data: function pointers to SoC-specific implementations of
92 for (i = 0; i < prcm_irq_setup->nr_regs; i++) { in omap_prcm_events_filter_priority()
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H A Dwd_timer.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * OMAP2+ MPU WD_TIMER-specific code
12 #include <linux/platform_data/omap-wd-timer.h>
23 * settings, WDT module is reset during init. This enables the watchdog
24 * timer. Hence it is required to disable the watchdog after the WDT reset
25 * during init. Otherwise the system would reboot as per the default
37 return -EINVAL; in omap2_wd_timer_disable()
43 oh->name, __func__); in omap2_wd_timer_disable()
44 return -EINVAL; in omap2_wd_timer_disable()
60 * omap2_wd_timer_reset - reset and disable the WDTIMER IP block
[all …]
H A Domap_hwmod.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2009-2011 Nokia Corporation
6 * Copyright (C) 2011-2012 Texas Instruments, Inc.
13 * These headers and macros are used to define OMAP on-chip module
16 * omap_hwmod code, in arch/arm/mach-omap2/omap_hwmod.c (as of this
20 * - add interconnect error log structures
21 * - init_conn_id_bit (CONNID_BIT_VECTOR)
22 * - implement default hwmod SMS/SDRC flags?
23 * - move Linux-specific data ("non-ROM data") out
29 #include <linux/init.h>
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/linux/Documentation/devicetree/bindings/bus/
H A Dti-sysc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/bus/ti-sysc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tony Lindgren <tony@atomide.com>
16 is mostly used for interaction between module and Power, Reset and Clock
31 pattern: "^target-module(@[0-9a-f]+)?$"
35 - items:
36 - enum:
37 - ti,sysc-omap2
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/linux/drivers/gpu/drm/i915/gt/
H A Dintel_reset.c1 // SPDX-License-Identifier: MIT
3 * Copyright © 2008-2018 Intel Corporation
41 struct drm_i915_file_private *file_priv = ctx->file_priv; in client_mark_guilty()
52 prev_hang = xchg(&file_priv->hang_timestamp, jiffies); in client_mark_guilty()
57 atomic_add(score, &file_priv->ban_score); in client_mark_guilty()
59 drm_dbg(&ctx->i915->drm, in client_mark_guilty()
61 ctx->name, score, in client_mark_guilty()
62 atomic_read(&file_priv->ban_score)); in client_mark_guilty()
73 if (intel_context_is_closed(rq->context)) in mark_guilty()
77 ctx = rcu_dereference(rq->context->gem_context); in mark_guilty()
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/linux/drivers/clk/
H A Dclk-gemini.c1 // SPDX-License-Identifier: GPL-2.0
7 #define pr_fmt(fmt) "clk-gemini: " fmt
9 #include <linux/init.h>
15 #include <linux/clk-provider.h>
21 #include <linux/reset-controller.h>
22 #include <dt-bindings/reset/cortina,gemini-reset.h>
23 #include <dt-bindings/clock/cortina,gemini-clock.h>
53 * struct gemini_gate_data - Gemini gated clocks
67 * struct clk_gemini_pci - Gemini PCI clock
77 * struct gemini_reset - gemini reset controller
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/linux/Documentation/devicetree/bindings/arm/omap/
H A Domap.txt5 On top of that an omap_device is created to extend the platform_device
11 to move data from hwmod to device-tree representation.
15 - compatible: Every devices present in OMAP SoC should be in the
17 - ti,hwmods: list of hwmod names (ascii strings), that comes from the OMAP
22 - ti,no_idle_on_suspend: When present, it prevents the PM to idle the module
24 - ti,no-reset-on-init: When present, the module should not be reset at init
25 - ti,no-idle-on-init: When present, the module should not be idled at init
26 - ti,no-idle: When present, the module is never allowed to idle.
31 compatible = "ti,omap4-spinlock";
37 - General Purpose devices
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/linux/drivers/crypto/intel/qat/qat_common/
H A Dadf_pfvf_pf_proto.c1 // SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only)
2 /* Copyright(c) 2015 - 2021 Intel Corporation */
16 NULL, /* no message type defined for value 0 */
17 NULL, /* no message type defined for value 1 */
23 * adf_send_pf2vf_msg() - send PF to VF message
30 * Return: 0 on success, error code otherwise.
35 u32 pfvf_offset = pfvf_ops->get_pf2vf_offset(vf_nr); in adf_send_pf2vf_msg()
37 return pfvf_ops->send_msg(accel_dev, msg, pfvf_offset, in adf_send_pf2vf_msg()
38 &accel_dev->pf.vf_info[vf_nr].pf2vf_lock); in adf_send_pf2vf_msg()
42 * adf_recv_vf2pf_msg() - receive a VF to PF message
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/linux/Documentation/hwmon/
H A Dw83791d.rst10 Addresses scanned: I2C 0x2c - 0x2f
12 Datasheet: http://www.winbond-usa.com/products/winbond_products/pdfs/PCIC/W83791D_W83791Gb.pdf
22 - Frodo Looijaard <frodol@dds.nl>,
23 - Philip Edelbrock <phil@netroedge.com>,
24 - Mark Studebaker <mdsxyz123@yahoo.com>
28 - Shane Huang (Winbond),
29 - Rudolf Marek <r.marek@assembler.cz>
33 - Sven Anders <anders@anduras.de>
34 - Marc Hulsman <m.hulsman@tudelft.nl>
37 -----------------
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/linux/drivers/firewire/
H A Dinit_ohci1394_dma.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * init_ohci1394_dma.c - Initializes physical DMA on all OHCI 1394 controllers
5 * Copyright (C) 2006-2007 Bernhard Kaindl <bk@suse.de>
7 * Derived from drivers/ieee1394/ohci1394.c and arch/x86/kernel/early-quirks.c
9 * - scan the PCI very early on boot for all OHCI 1394-compliant controllers
10 * - reset and initialize them and make them join the IEEE1394 bus and
11 * - enable physical DMA on them to allow remote debugging
18 * be sure that the stack enables it and (re-)attach after the bus reset
28 #include <asm/pci-direct.h> /* for direct PCI config space access */
42 writel(data, ohci->registers + offset); in reg_write()
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/linux/Documentation/devicetree/bindings/gpio/
H A Dti,omap-gpio.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/ti,omap-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Grygorii Strashko <grygorii.strashko@ti.com>
13 The general-purpose interface combines general-purpose input/output (GPIO) banks.
14 Each GPIO banks provides up to 32 dedicated general-purpose pins with input
15 and output capabilities; interrupt generation in active mode and wake-up
21 - enum:
22 - ti,omap2-gpio
[all …]
/linux/drivers/net/ethernet/intel/igc/
H A Digc_base.c1 // SPDX-License-Identifier: GPL-2.0
13 * igc_reset_hw_base - Reset hardware
24 /* Prevent the PCI-E bus from sticking if there is no TLP connection in igc_reset_hw_base()
25 * on the last TLP read/write transaction when MAC is reset. in igc_reset_hw_base()
29 hw_dbg("PCI-E Master disable polling has failed\n"); in igc_reset_hw_base()
42 hw_dbg("Issuing a global reset to MAC\n"); in igc_reset_hw_base()
49 * where there is no eeprom and prevents getting link. in igc_reset_hw_base()
62 * igc_init_nvm_params_base - Init NVM func ptrs.
67 struct igc_nvm_info *nvm = &hw->nvm; in igc_init_nvm_params_base()
73 return -ENXIO; in igc_init_nvm_params_base()
[all …]
/linux/include/linux/pds/
H A Dpds_core_if.h1 /* SPDX-License-Identifier: (GPL-2.0 OR Linux-OpenIB) OR BSD-2-Clause */
31 * enum pds_core_cmd_opcode - Device commands
34 /* Core init */
54 * enum pds_core_status_code - Device command return codes
64 PDS_RC_ENOENT = 7, /* No such element */
72 PDS_RC_ENOSPC = 15, /* No space left or alloc failure */
75 PDS_RC_DEV_CMD = 18, /* Device cmd attempted on AdminQ */
81 PDS_RC_ECLIENT = 33, /* No such client id */
86 * struct pds_core_drv_identity - Driver identity information
105 * struct pds_core_dev_identity - Device identity information
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/linux/Documentation/devicetree/bindings/sound/
H A Dcirrus,cs42l42.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - patches@opensource.cirrus.com
13 The CS42L42 is a low-power audio codec designed for portable applications.
14 It provides a high-dynamic range, stereo DAC for audio playback and a mono
15 high-dynamic-range ADC for audio capture. There is an integrated headset
21 - cirrus,cs42l42
22 - cirrus,cs42l83
29 VP-supply:
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/linux/net/dccp/
H A Dinput.c1 // SPDX-License-Identifier: GPL-2.0-or-later
19 /* rate-limit for syncs in reply to sequence-invalid packets; RFC 4340, 7.5.4 */
24 __skb_pull(skb, dccp_hdr(skb)->dccph_doff * 4); in dccp_enqueue_skb()
25 __skb_queue_tail(&sk->sk_receive_queue, skb); in dccp_enqueue_skb()
27 sk->sk_data_ready(sk); in dccp_enqueue_skb()
33 * On receiving Close/CloseReq, both RD/WR shutdown are performed. in dccp_fin()
35 * receiving the closing segment, but there is no guarantee that such in dccp_fin()
38 sk->sk_shutdown = SHUTDOWN_MASK; in dccp_fin()
47 switch (sk->sk_state) { in dccp_rcv_close()
50 * - CLOSED (may be a late or duplicate packet) in dccp_rcv_close()
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/linux/drivers/net/
H A Dsungem_phy.c1 // SPDX-License-Identifier: GPL-2.0-only
7 * (c) 2002-2007, Benjamin Herrenscmidt (benh@kernel.crashing.org)
10 * - Add support for PHYs that provide an IRQ line
11 * - Eventually moved the entire polling state machine in
13 * skipped on PHYs that implement it in hardware.
14 * - On LXT971 & BCM5201, Apple uses some chip specific regs
17 * - Apple has some additional power management code for some
37 { 0, 0, 0 }, /* No link */
49 return phy->mdio_read(phy->dev, id, reg); in __sungem_phy_read()
54 phy->mdio_write(phy->dev, id, reg, val); in __sungem_phy_write()
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/linux/drivers/phy/st/
H A Dphy-stih407-usb.c1 // SPDX-License-Identifier: GPL-2.0-only
17 #include <linux/reset.h>
44 reset_control_deassert(phy_dev->rstc); in stih407_usb2_pico_ctrl()
46 return regmap_update_bits(phy_dev->regmap, phy_dev->ctrl, in stih407_usb2_pico_ctrl()
58 ret = regmap_update_bits(phy_dev->regmap, in stih407_usb2_init_port()
59 phy_dev->param, in stih407_usb2_init_port()
65 return reset_control_deassert(phy_dev->rstport); in stih407_usb2_init_port()
73 * Only port reset is asserted, phy global reset is kept untouched in stih407_usb2_exit_port()
74 * as other ports may still be active. When all ports are in reset in stih407_usb2_exit_port()
75 * state, assumption is made that power will be cut off on the phy, in in stih407_usb2_exit_port()
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/linux/drivers/watchdog/
H A Dsmsc37b787_wdt.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Based on acquirewdt.c by Alan Cox <alan@lxorguk.ukuu.org.uk>
9 * any of this software. This material is provided "AS-IS" in
12 * (C) Copyright 2003-2006 Sven Anders <anders@anduras.de>
15 * 2003 - Created version 1.0 for Linux 2.4.x.
16 * 2006 - Ported to Linux 2.6, added nowayout and MAGICCLOSE
22 * reset the computer system in case of a software fault.
30 * for yet another little while to reset the system.
33 * reset the system (causing a reboot) after the timeout occurs.
38 * For an example userspace keep-alive daemon, see:
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/linux/include/linux/platform_data/
H A Dbrcmfmac.h10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
34 * Note: the brcmfmac can be loaded as module or be statically built-in into
35 * the kernel. If built-in then do note that it uses module_init (and
38 * it built-in to the kernel then use a higher initcall then device_initcall
39 * (see init.h). If this is not done then brcmfmac will load without problems
43 * without reporting anything and just assume there is no data needed. Which is
48 * enum brcmf_bus_type - Bus type identifier. Currently SDIO, USB and PCIE are
59 * struct brcmfmac_sdio_pd - SDIO Device specific platform data.
66 * which will be used depends on the capabilities of the
69 * in-band interrupts are relatively slow and for having
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/linux/drivers/media/pci/saa7134/
H A Dsaa7134-dvb.c1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * cards with the tda10046 DVB-T channel decoder
11 #include "saa7134-reg.h"
13 #include <linux/init.h>
21 #include <media/v4l2-common.h>
22 #include "dvb-pll.h"
38 #include "tuner-simple.h"
69 /* ------------------------------------------------------------------
70 * mt352 based DVB-T cards
73 static int pinnacle_antenna_pwr(struct saa7134_dev *dev, int on) in pinnacle_antenna_pwr() argument
[all …]
/linux/drivers/gpu/drm/i915/gt/uc/
H A Dintel_uc.h1 /* SPDX-License-Identifier: MIT */
3 * Copyright © 2014-2019 Intel Corporation
23 int (*init)(struct intel_uc *uc); member
61 * a subset of which is not cleaned on GT reset, will start expecting the GuC FW
64 * the relevant modparam is set and the blobs are found on the system. At this
65 * stage, the only thing that can stop us from attempting to load the blobs on
66 * the HW and use them is a fundamental issue (e.g. no memory for our
68 * without GuC, so there is no point in trying to fall back.
72 * - Not supported: not available in HW and/or firmware not defined.
73 * - Supported: available in HW and firmware defined.
[all …]
/linux/Documentation/PCI/
H A Dpci-error-recovery.rst1 .. SPDX-License-Identifier: GPL-2.0
8 :Authors: - Linas Vepstas <linasvepstas@gmail.com>
9 - Richard Lary <rlary@us.ibm.com>
10 - Mike Mason <mmlnx@us.ibm.com>
14 PCI errors on the bus, such as parity errors on the data and address
16 chipsets are able to deal with these errors; these include PCI-E chipsets,
17 and the PCI-host bridges found on IBM Power4, Power5 and Power6-based
22 offered, so that the affected PCI device(s) are reset and put back
23 into working condition. The reset phase requires coordination
32 including multiple instances of a device driver on multi-function
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