multiply\-accumulate (full) in projects: freebsd

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Searched +full:multiply +full:- +full:accumulate (Results 1 – 25 of 112) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A D	ARMISelLowering.h	1 //===- ARMISelLowering.h - ARM DAG Lowering Interface ------------ C++ --===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 12 //===----------------------------------------------------------------------===// 60 Wrapper, // Wrapper - A wrapper node for TargetConstantPool, 62 WrapperPIC, // WrapperPIC - A wrapper node for TargetGlobalAddress in 64 WrapperJT, // WrapperJT - A wrapper node for TargetJumpTable 71 CALL_NOLINK, // Function call with branch not branch-and-link. 72 tSECALL, // CMSE non-secure function call. 76 BR2_JT, // Jumptable branch (2 level - jumptable entry is a jump). [all …]
H A D	ARMScheduleA57.td	1 //=- ARMScheduleA57.td - ARM Cortex-A57 Scheduling Defs ------ tablegen --=// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 9 // This file defines the machine model for ARM Cortex-A57 to support 12 //===----------------------------------------------------------------------===// 14 //===----------------------------------------------------------------------===// 16 // The Cortex-A57 is a traditional superscalar microprocessor with a 17 // conservative 3-wide in-order stage for decode and dispatch. Combined with the 18 // much wider out-of-order issue stage, this produced a need to carefully 19 // schedule micro-ops so that all three decoded each cycle are successfully [all …]
H A D	ARMScheduleA8.td	1 //=- ARMScheduleA8.td - ARM Cortex-A8 Scheduling Definitions -- tablegen --=// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 11 //===----------------------------------------------------------------------===// 14 // Scheduling information derived from "Cortex-A8 Technical Reference Manual". 27 // Two fully-pipelined integer ALU pipelines 94 // Integer multiply pipeline 154 [1, 1, 1, 1, 3], [], -1>, // dynamic uops 159 [2, 1, 1, 1, 3], [], -1>, // dynamic uops 165 [1, 2, 1, 1, 3], [], -1>, // dynamic uops [all …]
H A D	ARMScheduleSwift.td	`1 //=- ARMScheduleSwift.td - Swift Scheduling Definitions -- tablegen -----===// 5 // SPDX-Licens [all...]`
H A D	ARMParallelDSP.cpp	1 //===- ARMParallelDSP.cpp - Parallel DSP Pass -----------------------------===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 10 /// Armv6 introduced instructions to perform 32-bit SIMD operations. The 12 /// DSP intrinsics, which map on these 32-bit SIMD operations. 15 //===----------------------------------------------------------------------===// 42 #define DEBUG_TYPE "arm-parallel-dsp" 47 DisableParallelDSP("disable-arm-parallel-dsp", cl::Hidden, cl::init(false), 51 NumLoadLimit("arm-parallel-dsp-load-limit", cl::Hidden, cl::init(16), 84 /// Represent a sequence of multiply-accumulate operations with the aim to [all …]
H A D	ARMSchedule.td	`1 //===-- ARMSchedule.td - ARM Scheduling Definitions ------- [all...]`
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A D	AArch64SchedA510.td	1 //==- AArch64SchedCortexA510.td - ARM Cortex-A510 Scheduling Definitions -- tablegen --=// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 9 // This file defines the machine model for the ARM Cortex-A510 processor. 11 //===----------------------------------------------------------------------===// 13 // ===---------------------------------------------------------------------===// 14 // The following definitions describe the per-operand machine model. 17 // Cortex-A510 machine model for scheduling and other instruction cost heuristics. 19 let MicroOpBufferSize = 0; // The Cortex-A510 is an in-order processor 20 let IssueWidth = 3; // It dual-issues under most circumstances [all …]
H A D	AArch64SchedNeoverseN2.td	1 //=- AArch64SchedNeoverseN2.td - NeoverseN2 Scheduling Defs --- tablegen --=// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 11 //===----------------------------------------------------------------------===// 14 let IssueWidth = 10; // Micro-ops dispatched at a time. 15 let MicroOpBufferSize = 160; // Entries in micro-op re-order buffer. 18 let LoopMicroOpBufferSize = 16; // NOTE: Copied from Cortex-A57. 25 //===----------------------------------------------------------------------===// 27 // Instructions are first fetched and then decoded into internal macro-ops 29 // stages. A MOP can be split into two micro-ops further down the pipeline [all …]
H A D	AArch64SchedNeoverseN1.td	`1 //=- AArch64SchedNeoverseN1.td - NeoverseN1 Scheduling Model -- tablegen --=// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exceptio [all...]`
H A D	AArch64SchedNeoverseV2.td	1 //=- AArch64SchedNeoverseV2.td - NeoverseV2 Scheduling Defs --- tablegen --=// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 12 // https://developer.arm.com/documentation/PJDOC-466751330-593177/r0p2 14 //===----------------------------------------------------------------------===// 17 let IssueWidth = 16; // Micro-ops dispatched at a time. 18 let MicroOpBufferSize = 320; // Entries in micro-op re-order buffer. 21 let LoopMicroOpBufferSize = 16; // NOTE: Copied from Cortex-A57. 29 //===----------------------------------------------------------------------===// 31 // Instructions are first fetched and then decoded into internal macro-ops [all …]
H A D	AArch64SchedNeoverseV1.td	1 //=- AArch64SchedNeoverseV1.td - NeoverseV1 Scheduling Model -- tablegen --=// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 12 // - "Arm Neoverse V1 Software Optimization Guide" 13 // - "Arm Neoverse V1 Platform: Unleashing a new performance tier for Arm-based computing" 14 …//community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/neoverse-v1-plat… 15 // - "Neoverse V1" 19 //===----------------------------------------------------------------------===// 22 let IssueWidth = 15; // Maximum micro-ops dispatch rate. 23 let MicroOpBufferSize = 256; // Micro-op re-order buffer. [all …]
H A D	AArch64SchedA57.td	`1 //=- AArch64SchedA57.td - ARM Cortex-A57 Scheduling Defs ------ tablegen - [all...]`
H A D	AArch64SchedThunderX2T99.td	`1 //=- AArch64SchedThunderX2T99.td - Cavium ThunderX T99 ---- tablegen --=// 5 // SPDX-License-Identifie [all...]`
H A D	AArch64SchedThunderX3T110.td	`1 //=- AArch64SchedThunderX3T110.td - Marvell ThunderX3 T110 ---- tablegen --=// 5 // SPDX-License-Identifie [all...]`
H A D	AArch64SchedA55.td	`1 //==- AArch64SchedCortexA55.td - ARM Cortex-A55 Scheduling Definitions -- tablegen --=// 5 // SPDX-License-Identifier: Apache-2. [all...]`
H A D	AArch64Schedule.td	1 //==-- AArch64Schedule.td - AArch64 Scheduling Definitions -- tablegen --===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 14 static_cast<const AArch64InstrInfo*>(SchedModel->getInstrInfo()); 25 def WriteISReg : SchedWrite; // ALU of Shifted-Reg 26 def WriteIEReg : SchedWrite; // ALU of Extended-Reg 28 def ReadISReg : SchedRead; // ALU of Shifted-Reg 29 def ReadIEReg : SchedRead; // ALU of Extended-Reg 33 def WriteID32 : SchedWrite; // 32-bit Divide 34 def WriteID64 : SchedWrite; // 64-bit Divide [all …]
H A D	AArch64SchedA64FX.td	`1 //=- AArch64SchedA64FX.td - Fujitsu A64FX Scheduling Defs -- tablegen --=// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exceptio [all...]`
H A D	AArch64A57FPLoadBalancing.cpp	`1 //===-- AArch64A57FPLoadBalancing.cpp - Balance FP ops statically on A57---===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exceptio [all...]`
H A D	AArch64A53Fix835769.cpp	1 //===-- AArch64A53Fix835769.cpp -------------------------------------------===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 8 // This pass changes code to work around Cortex-A53 erratum 835769. 13 // instr 1: mem-instr (including loads, stores and prefetches). 14 // instr 2: non-SIMD integer multiply-accumulate writing 64-bit X registers. 15 //===----------------------------------------------------------------------===// 31 #define DEBUG_TYPE "aarch64-fix-cortex-a53-835769" 35 //===----------------------------------------------------------------------===// 42 switch (MI->getOpcode()) { in isFirstInstructionInSequence() [all …]
H A D	AArch64SchedTSV110.td	1 //==- AArch64SchedTSV110.td - Huawei TSV110 Scheduling Definitions -- tablegen --=// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 12 //===----------------------------------------------------------------------===// 14 // ===---------------------------------------------------------------------===// 15 // The following definitions describe the simpler per-operand machine model. 20 let IssueWidth = 4; // 4 micro-ops dispatched per cycle. 21 let MicroOpBufferSize = 128; // 128 micro-op re-order buffer 34 // which has 8 pipelines, each with its own queue where micro-ops wait for 35 // their operands and issue out-of-order to one of eight execution pipelines. [all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A D	RISCVFeatures.td	1 //===-- RISCVFeatures.td - RISC-V Features and Extensions --- tablegen --===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 9 //===----------------------------------------------------------------------===// 10 // RISC-V subtarget features and instruction predicates. 11 //===----------------------------------------------------------------------===// 13 // Subclass of SubtargetFeature to be used when the feature is also a RISC-V 16 // name - Name of the extension in lower case. 17 // major - Major version of extension. 18 // minor - Minor version of extension. [all …]
/freebsd/sys/contrib/device-tree/Bindings/riscv/
H A D	extensions.yaml	`1 # SPDX-License-Identifier: (GPL-2.0 OR MIT) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: RISC-V ISA extensions 10 - Paul Walmsley <paul.walmsley@sifive.com> 11 - Palmer Dabbelt <palmer@sifive.com> 12 - Conor Dooley <conor@kernel.org> 15 RISC-V has a large number of extensions, some of which are "standard" 16 extensions, meaning they are ratified by RISC-V International, and others 36 Identifies the specific RISC-V instruction set architecture [all …]`
/freebsd/lib/libpmc/pmu-events/arch/x86/amdzen3/
H A D	floating-point.json	6 … Each increment represents a one- cycle dispatch event. This event is a speculative event. Since t… 13 … Each increment represents a one-cycle dispatch event. This event is a speculative event. Since th… 20 … Each increment represents a one- cycle dispatch event. This event is a speculative event. Since t… 27 … Each increment represents a one- cycle dispatch event. This event is a speculative event. Since t… 34 … Each increment represents a one- cycle dispatch event. This event is a speculative event. Since t… 40 …"BriefDescription": "All FLOPS. This is a retire-based event. The number of retired SSE/AVX FLOPS.… 46 …"BriefDescription": "Multiply-Accumulate FLOPs. Each MAC operation is counted as 2 FLOPS. This is … 52 …"BriefDescription": "Divide/square root FLOPs. This is a retire-based event. The number of retired… 58 …"BriefDescription": "Multiply FLOPs. This is a retire-based event. The number of retired SSE/AVX F… 64 …"BriefDescription": "Add/subtract FLOPs. This is a retire-based event. The number of retired SSE/A… [all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A D	HexagonIntrinsicsV5.td	1 //===- HexagonIntrinsicsV5.td - V5 Instruction intrinsics --- tablegen --===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 23 // Vector reduce multiply word by signed half (32x16) 40 // Vector multiply halfwords, signed by unsigned 49 // Vector polynomial multiply halfwords 55 // Polynomial multiply words 70 // Multiply and use upper result 128 // Complex multiply 32x16 194 // ALU64 - Vector min/max byte [all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A D	PPCRegisterInfoMMA.td	1 //===-- PPCRegisterInfoMMA.td - The PowerPC Register File --- tablegen --===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 12 //===----------------------------------------------------------------------===// 19 // ACC - One of the 8 512-bit VSX accumulators. 21 let HWEncoding{2-0} = num; 25 // UACC - One of the 8 512-bit VSX accumulators prior to being primed. 30 let HWEncoding{2-0} = num; 34 // SPE Accumulator for multiply-accumulate SPE operations. Never directly 39 def ACC0 : ACC<0, "acc0", [VSRp0, VSRp1]>, DwarfRegNum<[-1, -1]>; [all …]

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