Lines Matching +full:multiply +full:- +full:accumulate
1 //=- AArch64SchedThunderX2T99.td - Cavium ThunderX T99 ---*- tablegen -*-=//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
19 let IssueWidth = 4; // 4 micro-ops dispatched at a time.
20 let MicroOpBufferSize = 180; // 180 entries in micro-op re-order buffer.
23 // Determined via a mix of micro-arch details and experimentation.
65 // Integer divide and multiply micro-ops only on port 1.
68 // Branch micro-ops only on port 2.
71 // ALU micro-ops on ports 0, 1, and 2.
74 // Crypto FP/SIMD micro-ops only on port 1.
77 // FP/SIMD micro-ops on ports 0 and 1.
80 // Store data micro-ops only on port 3.
83 // Load/store micro-ops on ports 4 and 5.
368 //===----------------------------------------------------------------------===//
371 //---
373 //---
400 //---
402 //---
409 //---
412 //---
497 //---
498 // 3.4 Divide and Multiply Instructions
499 //---
501 // Divide, W-form
502 // Latency range of 13-23/13-39.
509 // Divide, X-form
516 // Multiply accumulate, W-form
522 // Multiply accumulate, X-form
544 // Multiply high
547 // Miscellaneous Data-Processing Instructions
551 // Bitifield move - basic
587 //---
590 //---
601 // Load register, immed post-index
603 // Load register, immed pre-index
613 // LDP only breaks into *one* LS micro-op. Thus
636 // Load pair, immed pre-index, normal
637 // Load pair, immed pre-index, signed words
638 // Load pair, immed post-index, normal
639 // Load pair, immed post-index, signed words
848 //---
850 //---
857 //--
860 //--
870 // Store register, immed post-index
873 // Store register, immed pre-index
887 // Store pair, immed offset, W-form
888 // Store pair, immed offset, X-form
894 // Store pair, immed post-index, W-form
895 // Store pair, immed post-index, X-form
896 // Store pair, immed pre-index, W-form
897 // Store pair, immed pre-index, X-form
1089 //---
1091 //---
1146 // FP divide, S-form
1147 // FP square root, S-form
1154 // FP divide, D-form
1155 // FP square root, D-form
1162 // FP multiply
1163 // FP multiply accumulate
1193 //---
1195 //---
1221 //---
1223 //---
1225 // ASIMD absolute diff, D-form
1226 // ASIMD absolute diff, Q-form
1227 // ASIMD absolute diff accum, D-form
1228 // ASIMD absolute diff accum, Q-form
1239 // ASIMD multiply, D-form
1240 // ASIMD multiply, Q-form
1241 // ASIMD multiply accumulate long
1242 // ASIMD multiply accumulate saturating long
1243 // ASIMD multiply long
1244 // ASIMD pairwise add and accumulate
1245 // ASIMD shift accumulate
1247 // ASIMD shift by immed and insert, basic, D-form
1248 // ASIMD shift by immed and insert, basic, Q-form
1250 // ASIMD shift by register, basic, D-form
1251 // ASIMD shift by register, basic, Q-form
1252 // ASIMD shift by register, complex, D-form
1253 // ASIMD shift by register, complex, Q-form
1277 // ASIMD polynomial (8x8) multiply long
1284 // ASIMD absolute diff accum, D-form
1287 // ASIMD absolute diff accum, Q-form
1311 // ASIMD multiply, D-form
1316 // ASIMD multiply, Q-form
1319 // ASIMD multiply accumulate, D-form
1322 // ASIMD multiply accumulate, Q-form
1325 // ASIMD shift accumulate
1337 // ASIMD shift by register, basic, Q-form
1340 // ASIMD shift by register, complex, D-form
1344 // ASIMD shift by register, complex, Q-form
1389 //---
1390 // 3.13 ASIMD Floating-point Instructions
1391 //---
1396 // ASIMD FP arith, normal, D-form
1397 // ASIMD FP arith, normal, Q-form
1401 // ASIMD FP arith,pairwise, D-form
1402 // ASIMD FP arith, pairwise, Q-form
1405 // ASIMD FP compare, D-form
1406 // ASIMD FP compare, Q-form
1412 // ASIMD FP round, D-form
1415 // ASIMD FP round, Q-form
1421 // ASIMD FP convert, other, D-form
1422 // ASIMD FP convert, other, Q-form
1427 // ASIMD FP convert, other, D-form
1430 // ASIMD FP convert, other, Q-form
1434 // ASIMD FP divide, D-form, F32
1438 // ASIMD FP divide, Q-form, F32
1442 // ASIMD FP divide, Q-form, F64
1446 // ASIMD FP max/min, normal, D-form
1447 // ASIMD FP max/min, normal, Q-form
1451 // ASIMD FP max/min, pairwise, D-form
1452 // ASIMD FP max/min, pairwise, Q-form
1460 // ASIMD FP multiply, D-form, FZ
1461 // ASIMD FP multiply, D-form, no FZ
1462 // ASIMD FP multiply, Q-form, FZ
1463 // ASIMD FP multiply, Q-form, no FZ
1470 // ASIMD FP multiply accumulate, Dform, FZ
1471 // ASIMD FP multiply accumulate, Dform, no FZ
1472 // ASIMD FP multiply accumulate, Qform, FZ
1473 // ASIMD FP multiply accumulate, Qform, no FZ
1483 //--
1485 //--
1490 // ASIMD bitwise insert, D-form
1491 // ASIMD bitwise insert, Q-form
1495 // ASIMD count, D-form
1496 // ASIMD count, Q-form
1528 // ASIMD reciprocal estimate, D-form
1529 // ASIMD reciprocal estimate, Q-form
1534 // ASIMD reciprocal step, D-form, FZ
1535 // ASIMD reciprocal step, D-form, no FZ
1536 // ASIMD reciprocal step, Q-form, FZ
1537 // ASIMD reciprocal step, Q-form, no FZ
1544 // ASIMD table lookup, D-form
1545 // ASIMD table lookup, Q-form
1564 //--
1566 //--
1568 // ASIMD load, 1 element, multiple, 1 reg, D-form
1569 // ASIMD load, 1 element, multiple, 1 reg, Q-form
1575 // ASIMD load, 1 element, multiple, 2 reg, D-form
1576 // ASIMD load, 1 element, multiple, 2 reg, Q-form
1582 // ASIMD load, 1 element, multiple, 3 reg, D-form
1583 // ASIMD load, 1 element, multiple, 3 reg, Q-form
1589 // ASIMD load, 1 element, multiple, 4 reg, D-form
1590 // ASIMD load, 1 element, multiple, 4 reg, Q-form
1602 // ASIMD load, 1 element, all lanes, D-form, B/H/S
1603 // ASIMD load, 1 element, all lanes, D-form, D
1604 // ASIMD load, 1 element, all lanes, Q-form
1610 // ASIMD load, 2 element, multiple, D-form, B/H/S
1611 // ASIMD load, 2 element, multiple, Q-form, D
1624 // ASIMD load, 2 element, all lanes, D-form, B/H/S
1625 // ASIMD load, 2 element, all lanes, D-form, D
1626 // ASIMD load, 2 element, all lanes, Q-form
1632 // ASIMD load, 3 element, multiple, D-form, B/H/S
1633 // ASIMD load, 3 element, multiple, Q-form, B/H/S
1634 // ASIMD load, 3 element, multiple, Q-form, D
1647 // ASIMD load, 3 element, all lanes, D-form, B/H/S
1648 // ASIMD load, 3 element, all lanes, D-form, D
1649 // ASIMD load, 3 element, all lanes, Q-form, B/H/S
1650 // ASIMD load, 3 element, all lanes, Q-form, D
1656 // ASIMD load, 4 element, multiple, D-form, B/H/S
1657 // ASIMD load, 4 element, multiple, Q-form, B/H/S
1658 // ASIMD load, 4 element, multiple, Q-form, D
1671 // ASIMD load, 4 element, all lanes, D-form, B/H/S
1672 // ASIMD load, 4 element, all lanes, D-form, D
1673 // ASIMD load, 4 element, all lanes, Q-form, B/H/S
1674 // ASIMD load, 4 element, all lanes, Q-form, D
1680 //--
1682 //--
1684 // ASIMD store, 1 element, multiple, 1 reg, D-form
1685 // ASIMD store, 1 element, multiple, 1 reg, Q-form
1691 // ASIMD store, 1 element, multiple, 2 reg, D-form
1692 // ASIMD store, 1 element, multiple, 2 reg, Q-form
1698 // ASIMD store, 1 element, multiple, 3 reg, D-form
1699 // ASIMD store, 1 element, multiple, 3 reg, Q-form
1705 // ASIMD store, 1 element, multiple, 4 reg, D-form
1706 // ASIMD store, 1 element, multiple, 4 reg, Q-form
1719 // ASIMD store, 2 element, multiple, D-form, B/H/S
1720 // ASIMD store, 2 element, multiple, Q-form, B/H/S
1721 // ASIMD store, 2 element, multiple, Q-form, D
1734 // ASIMD store, 3 element, multiple, D-form, B/H/S
1735 // ASIMD store, 3 element, multiple, Q-form, B/H/S
1736 // ASIMD store, 3 element, multiple, Q-form, D
1749 // ASIMD store, 4 element, multiple, D-form, B/H/S
1750 // ASIMD store, 4 element, multiple, Q-form, B/H/S
1751 // ASIMD store, 4 element, multiple, Q-form, D