Lines Matching +full:multiply +full:- +full:accumulate
1 //=- AArch64SchedA57.td - ARM Cortex-A57 Scheduling Defs -----*- tablegen -*-=//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file defines the machine model for ARM Cortex-A57 to support
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // The Cortex-A57 is a traditional superscalar microprocessor with a
16 // conservative 3-wide in-order stage for decode and dispatch. Combined with the
17 // much wider out-of-order issue stage, this produced a need to carefully
18 // schedule micro-ops so that all three decoded each cycle are successfully
21 // modeling the machine as out-of-order.
24 let IssueWidth = 3; // 3-way decode and dispatch
25 let MicroOpBufferSize = 128; // 128 micro-op re-order buffer
40 //===----------------------------------------------------------------------===//
41 // Define each kind of processor resource and number available on Cortex-A57.
42 // Cortex A-57 has 8 pipelines that each has its own 8-entry queue where
43 // micro-ops wait for their operands and then issue out-of-order.
45 def A57UnitB : ProcResource<1>; // Type B micro-ops
46 def A57UnitI : ProcResource<2>; // Type I micro-ops
47 def A57UnitM : ProcResource<1>; // Type M micro-ops
48 def A57UnitL : ProcResource<1>; // Type L micro-ops
49 def A57UnitS : ProcResource<1>; // Type S micro-ops
50 def A57UnitX : ProcResource<1>; // Type X micro-ops
51 def A57UnitW : ProcResource<1>; // Type W micro-ops
53 def A57UnitV : ProcResGroup<[A57UnitX, A57UnitW]>; // Type V micro-ops
58 //===----------------------------------------------------------------------===//
59 // Define customized scheduler read/write types specific to the Cortex-A57.
63 //===----------------------------------------------------------------------===//
64 // Map the target-defined scheduler read/write resources and latency for
65 // Cortex-A57. The Cortex-A57 types are directly associated with resources, so
113 // Forwarding logic is only modeled for multiply and accumulate
126 //===----------------------------------------------------------------------===//
128 // subtarget-defined types. As the modeled is refined, this will override most
132 // -----------------------------------------------------------------------------
138 // -----------------------------------------------------------------------------
145 // ----------------------------------------------------------------------------
153 // Divide and Multiply Instructions
154 // -----------------------------------------------------------------------------
156 // Multiply high
160 // Miscellaneous Data-Processing Instructions
161 // -----------------------------------------------------------------------------
169 // -----------------------------------------------------------------------------
183 // -----------------------------------------------------------------------------
282 // -----------------------------------------------------------------------------
346 // Vector - Integer
347 // -----------------------------------------------------------------------------
350 // D form - v8i8, v4i16, v2i32
351 // Q form - v16i8, v8i16, v4i32
352 // D form - v1i8, v1i16, v1i32, v1i64
353 // Q form - v16i8, v8i16, v4i32, v2i64
354 // D form - v8i8_v8i16, v4i16_v4i32, v2i32_v2i64
355 // Q form - v16i8_v8i16, v8i16_v4i32, v4i32_v2i64
358 // Advance for absolute diff accum, pairwise add and accumulate, shift accumulate
361 // ASIMD absolute diff accum, D-form
363 // ASIMD absolute diff accum, Q-form
382 // ASIMD multiply, D-form
388 // ASIMD multiply, Q-form
398 // ASIMD multiply accumulate, D-form
400 // ASIMD multiply accumulate, Q-form
403 // ASIMD multiply accumulate long
404 // ASIMD multiply accumulate saturating long
408 // ASIMD multiply long
414 // ASIMD pairwise add and accumulate
415 // ASIMD shift accumulate
424 // ASIMD shift by register, basic, Q-form
427 // ASIMD shift by register, complex, D-form
430 // ASIMD shift by register, complex, Q-form
434 // Vector - Floating Point
435 // -----------------------------------------------------------------------------
438 // D form - v2f32
439 // Q form - v4f32, v2f64
440 // D form - 32, 64
441 // D form - v1i32, v1i64
442 // D form - v2i32
443 // Q form - v4i32, v2i64
445 // ASIMD FP arith, normal, D-form
447 // ASIMD FP arith, normal, Q-form
450 // ASIMD FP arith, pairwise, D-form
452 // ASIMD FP arith, pairwise, Q-form
455 // ASIMD FP compare, D-form
457 // ASIMD FP compare, Q-form
462 // ASIMD FP convert, other, D-form
464 // ASIMD FP convert, other, Q-form
467 // ASIMD FP divide, D-form, F32
469 // ASIMD FP divide, Q-form, F32
471 // ASIMD FP divide, Q-form, F64
475 // ASIMD FP square root, D-form, F32
477 // ASIMD FP square root, Q-form, F32
479 // ASIMD FP square root, Q-form, F64
482 // ASIMD FP max/min, normal, D-form
484 // ASIMD FP max/min, normal, Q-form
486 // ASIMD FP max/min, pairwise, D-form
488 // ASIMD FP max/min, pairwise, Q-form
493 // ASIMD FP multiply, D-form, FZ
495 // ASIMD FP multiply, Q-form, FZ
498 // ASIMD FP multiply accumulate, D-form, FZ
499 // ASIMD FP multiply accumulate, Q-form, FZ
504 // Advances from FP mul and mul-accum to mul-accum
511 // ASIMD FP round, D-form
513 // ASIMD FP round, Q-form
517 // Vector - Miscellaneous
518 // -----------------------------------------------------------------------------
521 // D form - v8i8, v4i16, v2i32
522 // Q form - v16i8, v8i16, v4i32
523 // D form - v1i8, v1i16, v1i32, v1i64
524 // Q form - v16i8, v8i16, v4i32, v2i64
526 // ASIMD bitwise insert, Q-form
529 // ASIMD duplicate, gen reg, D-form and Q-form
536 // ASIMD reciprocal estimate, D-form
538 // ASIMD reciprocal estimate, Q-form
541 // ASIMD reciprocal step, D-form, FZ
543 // ASIMD reciprocal step, Q-form, FZ
546 // ASIMD table lookup, D-form
551 // ASIMD table lookup, Q-form
563 // ASIMD unzip/zip, Q-form
568 // -----------------------------------------------------------------------------