Home
last modified time | relevance | path

Searched +full:multi +full:- +full:processors (Results 1 – 25 of 96) sorted by relevance

1234

/linux/Documentation/hwmon/
H A Dfam15h_power.rst6 * AMD Family 15h Processors
8 * AMD Family 16h Processors
16 - BIOS and Kernel Developer's Guide (BKDG) For AMD Family 15h Processors
17 - BIOS and Kernel Developer's Guide (BKDG) For AMD Family 16h Processors
18 - AMD64 Architecture Programmer's Manual Volume 2: System Programming
23 -----------
33 of AMD Family 15h and 16h processors via TDP algorithm.
35 For AMD Family 15h and 16h processors the following power values can
55 On multi-node processors the calculated value is for the entire
57 attributes only for internal node0 of a multi-node processor.
[all …]
/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dcsky,mpintc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/csky,mpintc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: C-SKY Multi-processors Interrupt Controller
10 - Guo Ren <guoren@kernel.org>
13 C-SKY Multi-processors Interrupt Controller is designed for ck807/ck810/ck860
14 SMP soc, and it also could be used in non-SMP system.
17 0-15 : software irq, and we use 15 as our IPI_IRQ.
18 16-31 : private irq, and we use 16 as the co-processor timer.
[all …]
/linux/Documentation/devicetree/bindings/timer/
H A Dcsky,mptimer.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: C-SKY Multi-processors Timer
10 - Flavio Suligoi <f.suligoi@asem.it>
11 - Guo Ren <guoren@kernel.org>
14 C-SKY multi-processors timer is designed for C-SKY SMP system and the regs are
15 accessed by cpu co-processor 4 registers with mtcr/mfcr.
17 - PTIM_CTLR "cr<0, 14>" Control reg to start reset timer.
18 - PTIM_TSR "cr<1, 14>" Interrupt cleanup status reg.
[all …]
/linux/arch/sh/mm/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
12 Some SH processors (such as SH-2/SH-2A) lack an MMU. In order to
15 On other systems (such as the SH-3 and 4) where an MMU exists,
26 On MMU-less systems, any of these page sizes can be selected
56 Computers built with Hitachi SuperH processors always
89 bool "Support 32-bit physical addressing through PMB"
95 32-bits through the SH-4A PMB. If this is not set, legacy
96 29-bit physical addressing will be used.
116 bool "Non-Uniform Memory Access (NUMA) Support"
186 bool "Multi-core scheduler support"
[all …]
/linux/Documentation/admin-guide/hw-vuln/
H A Dvmscape.rst1 .. SPDX-License-Identifier: GPL-2.0
10 guest-userspace may be able to attack the guest-kernel using the hypervisor as
13 Affected processors
14 -------------------
18 **Intel processors:**
19 - Skylake generation (Parts without Enhanced-IBRS)
20 - Cascade Lake generation - (Parts affected by ITS guest/host separation)
21 - Alder Lake and newer (Parts affected by BHI)
26 **AMD processors:**
27 - Zen series (families 0x17, 0x19, 0x1a)
[all …]
H A Dtsx_async_abort.rst1 .. SPDX-License-Identifier: GPL-2.0
3 TAA - TSX Asynchronous Abort
10 Affected processors
11 -------------------
13 This vulnerability only affects Intel processors that support Intel
15 is 0 in the IA32_ARCH_CAPABILITIES MSR. On processors where the MDS_NO bit
23 ------------
28 CVE-2019-11135 TAA TSX Asynchronous Abort (TAA) condition on some
36 -------
38 When performing store, load or L1 refill operations, processors write
[all …]
H A Dl1tf.rst1 L1TF - L1 Terminal Fault
9 Affected processors
10 -------------------
12 This vulnerability affects a wide range of Intel processors. The
15 - Processors from AMD, Centaur and other non Intel vendors
17 - Older processor models, where the CPU family is < 6
19 - A range of Intel ATOM processors (Cedarview, Cloverview, Lincroft,
22 - The Intel XEON PHI family
24 - Intel processors which have the ARCH_CAP_RDCL_NO bit set in the
33 ------------
[all …]
/linux/Documentation/arch/arm/
H A Dmarvell.rst13 ------------
16 - 88F5082
17 - 88F5181 a.k.a Orion-1
18 - 88F5181L a.k.a Orion-VoIP
19 - 88F5182 a.k.a Orion-NAS
21 …- Datasheet: https://web.archive.org/web/20210124231420/http://csclub.uwaterloo.ca/~board/ts7800/M…
22 …- Programmer's User Guide: https://web.archive.org/web/20210124231536/http://csclub.uwaterloo.ca/~…
23 …- User Manual: https://web.archive.org/web/20210124231631/http://csclub.uwaterloo.ca/~board/ts7800…
24 …- Functional Errata: https://web.archive.org/web/20210704165540/https://www.digriz.org.uk/ts78xx/8…
25 - 88F5281 a.k.a Orion-2
[all …]
/linux/Documentation/arch/powerpc/
H A Dcpu_features.rst8 This document describes the system (including self-modifying code) used in the
10 compile-time selection.
17 Detection of the feature set is simple. A list of processors can be found in
23 C code may test 'cur_cpu_spec[smp_processor_id()]->cpu_features' for a
28 several paths that are performance-critical and would suffer if an array
30 performance penalty but still allow for runtime (rather than compile-time) CPU
32 based on CPU 0's capabilities, so a multi-processor system with non-identical
33 processors will not work (but such a system would likely have other problems
53 cur_cpu_spec[0]->cpu_features) or is cleared, respectively. These two macros
/linux/arch/powerpc/platforms/
H A DKconfig.cputype1 # SPDX-License-Identifier: GPL-2.0
7 bool "64-bit kernel"
10 This option selects whether a 32-bit or a 64-bit kernel
61 Provide support for processors based on the 603 cores. Those
62 processors don't have a HASH MMU and provide SW TLB loading.
69 Provide support for processors not based on the 603 cores.
70 Those processors have a HASH MMU.
80 The other are the "embedded" processors compliant with the
84 bool "Server processors"
98 bool "Embedded processors"
[all …]
/linux/Documentation/devicetree/bindings/powerpc/nintendo/
H A Dwii.txt11 - model : Should be "nintendo,wii"
12 - compatible : Should be "nintendo,wii"
16 This node represents the multi-function "Hollywood" chip, which packages
21 - compatible : Should be "nintendo,hollywood"
30 - compatible : should be "nintendo,hollywood-vi","nintendo,flipper-vi"
31 - reg : should contain the VI registers location and length
32 - interrupts : should contain the VI interrupt
41 - compatible : should be "nintendo,hollywood-pi","nintendo,flipper-pi"
42 - reg : should contain the PI registers location and length
52 - #interrupt-cells : <1>
[all …]
/linux/Documentation/devicetree/bindings/soc/ti/
H A Dkeystone-navigator-qmss.txt5 multi-core Navigator. QMSS consist of queue managers, packed-data structure
6 processors(PDSP), linking RAM, descriptor pools and infrastructure
9 management of the packet queues. Packets are queued/de-queued by writing or
20 - compatible : Must be "ti,keystone-navigator-qmss".
21 : Must be "ti,66ak2g-navss-qm" for QMSS on K2G SoC.
22 - clocks : phandle to the reference clock for this device.
23 - queue-range : <start number> total range of queue numbers for the device.
24 - linkram0 : <address size> for internal link ram, where size is the total
26 - linkram1 : <address size> for external link ram, where size is the total
29 - qmgrs : child node describing the individual queue managers on the
[all …]
/linux/Documentation/block/
H A Dblk-mq.rst1 .. SPDX-License-Identifier: GPL-2.0
4 Multi-Queue Block IO Queueing Mechanism (blk-mq)
7 The Multi-Queue Block IO Queueing Mechanism is an API to enable fast storage
16 ----------
26 However, with the development of Solid State Drives and Non-Volatile Memories
30 in those devices' design, the multi-queue mechanism was introduced.
34 bottleneck of having a single lock for multiple processors. This setup also
36 to different CPUs) wanted to perform block IO. Instead of this, the blk-mq API
42 ---------
45 for instance), blk-mq takes action: it will store and manage IO requests to
[all …]
/linux/Documentation/arch/arm/pxa/
H A Dmfp.rst2 MFP Configuration for PXA2xx/PXA3xx Processors
7 MFP stands for Multi-Function Pin, which is the pin-mux logic on PXA3xx and
8 later PXA series processors. This document describes the existing MFP API,
15 mechanism is introduced from PXA3xx to completely move the pin-mux functions
16 out of the GPIO controller. In addition to pin-mux configurations, the MFP
17 also controls the low power state, driving strength, pull-up/down and event
21 +--------+
22 | |--(GPIO19)--+
24 | |--(GPIO...) |
25 +--------+ |
[all …]
/linux/arch/mips/include/asm/
H A Dcpu.h1 /* SPDX-License-Identifier: GPL-2.0 */
18 +----------------+----------------+----------------+----------------+
20 +----------------+----------------+----------------+----------------+
23 I don't have docs for all the previous processors, but my impression is
24 that bits 16-23 have been 0 for all MIPS processors before the MIPS32/64
92 #define PRID_IMP_LOONGSON_32 0x4200 /* Loongson-1 */
95 #define PRID_IMP_LOONGSON_64R 0x6100 /* Reduced Loongson-2 */
96 #define PRID_IMP_LOONGSON_64C 0x6300 /* Classic Loongson-2 and Loongson-3 */
97 #define PRID_IMP_LOONGSON_64G 0xc000 /* Generic Loongson-2 and Loongson-3 */
232 * Definitions for 7:0 on legacy processors
[all …]
/linux/Documentation/arch/x86/
H A Dtopology.rst1 .. SPDX-License-Identifier: GPL-2.0
11 The architecture-agnostic topology definitions are in
12 Documentation/admin-guide/cputopology.rst. This file holds x86-specific
17 Needless to say, code should use the generic functions - this file is *only*
29 advent of Multi Chip Modules (MCM) a socket can hold more than one package. So
35 - packages
36 - cores
37 - threads
48 Package-related topology information in the kernel:
50 - topology_num_threads_per_package()
[all …]
/linux/Documentation/devicetree/bindings/display/mediatek/
H A Dmediatek,padding.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chun-Kuang Hu <chunkuang.hu@kernel.org>
11 - Philipp Zabel <p.zabel@pengutronix.de>
16 width of a layer to be 2-pixel-align, or 4-pixel-align when ETHDR is enabled,
24 - enum:
25 - mediatek,mt8188-disp-padding
26 - mediatek,mt8195-mdp3-padding
27 - items:
[all …]
/linux/Documentation/virt/kvm/x86/
H A Dtimekeeping.rst1 .. SPDX-License-Identifier: GPL-2.0
4 Timekeeping Virtualization for X86-Based Architectures
32 information relevant to KVM and hardware-based virtualization.
41 2.1. i8254 - PIT
42 ----------------
46 channels which can be programmed to deliver periodic or one-shot interrupts.
53 The PIT uses I/O ports 0x40 - 0x43. Access to the 16-bit counters is done
59 -------------- ----------------
61 | 1.1932 MHz|---------->| CLOCK OUT | ---------> IRQ 0
63 -------------- | +->| GATE TIMER 0 |
[all …]
/linux/Documentation/arch/arm/keystone/
H A Dknav-qmss.rst11 multi-core Navigator. QMSS consist of queue managers, packed-data structure
12 processors(PDSP), linking RAM, descriptor pools and infrastructure
15 management of the packet queues. Packets are queued/de-queued by writing or
29 Documentation/devicetree/bindings/soc/ti/keystone-navigator-qmss.txt
40 git://git.ti.com/keystone-rtos/qmss-lld.git
43 channels. This firmware is available under ti-keystone folder of
46 git://git.kernel.org/pub/scm/linux/kernel/git/firmware/linux-firmware.git
/linux/drivers/clocksource/
H A Dtimer-mp-csky.c1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
11 #include "timer-of.h"
68 to->clkevt.event_handler(&to->clkevt); in csky_timer_interrupt()
80 to->clkevt.cpumask = cpumask_of(cpu); in csky_mptimer_starting_cpu()
84 clockevents_config_and_register(&to->clkevt, timer_of_rate(to), in csky_mptimer_starting_cpu()
124 * Csky_mptimer is designed for C-SKY SMP multi-processors and in csky_mptimer_init()
129 * mmio map style. So we needn't mmio-address in dts, but we still in csky_mptimer_init()
137 return -EINVAL; in csky_mptimer_init()
142 return -EINVAL; in csky_mptimer_init()
[all …]
/linux/arch/powerpc/kernel/
H A Dpaca.c1 // SPDX-License-Identifier: GPL-2.0-or-later
34 * Set bottom-up mode, because the boot CPU should be on node-0, in alloc_paca_data()
165 s->persistent = cpu_to_be32(SLB_NUM_BOLTED); in new_slb_shadow()
166 s->buffer_length = cpu_to_be32(sizeof(*s)); in new_slb_shadow()
175 * On systems with hardware multi-threading, there are two threads
177 * The VPD Areas will give a max logical processors = 2 * max physical
178 * processors. The processor VPD array needs one entry per physical
187 new_paca->lppaca_ptr = NULL; in initialise_paca()
190 new_paca->kernel_pgd = swapper_pg_dir; in initialise_paca()
192 new_paca->lock_token = 0x8000; in initialise_paca()
[all …]
/linux/Documentation/devicetree/bindings/soc/qcom/
H A Dqcom,saw2.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andy Gross <agross@kernel.org>
11 - Bjorn Andersson <bjorn.andersson@linaro.org>
19 power-controller that transitions a piece of hardware (like a processor or
21 the PMIC. It can also be wired up to interact with other processors in the
27 - enum:
28 - qcom,ipq4019-saw2-cpu
29 - qcom,ipq4019-saw2-l2
[all …]
/linux/sound/oss/dmasound/
H A Ddmasound.h1 /* SPDX-License-Identifier: GPL-2.0 */
11 * device for true DSP processors but it will be called something else.
69 #define MIN_BUFSIZE (1<<12) /* in bytes (- where does this come from ?) */
72 #define MAX_FRAG_SIZE 15 /* allow *4 for mono-8 => stereo-16 (for multi) */
74 #else /* is pmac and multi is off */
80 #define MAX_FRAG_SIZE 16 /* need to allow *4 for mono-8 => stereo-16 */
93 /* description of the set-up applies to either hard or soft settings */
135 int capabilities ; /* low-level reply to SNDCTL_DSP_GETCAPS */
218 int max_active; /* in-use fragments <= max_count */
245 /* define the value to be put in the byte-swap reg in mac-io
/linux/arch/arm/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
162 The ARM series is a line of low-power-consumption RISC chip designs
164 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
165 manufactured, but legacy ARM-based PC hardware remains popular in
173 relocations. The combined range is -/+ 256 MiB, which is usually
266 Patch phys-to-virt and virt-to-phys translation functions at
270 This can only be used with non-XIP MMU kernels where the base
316 bool "MMU-based Paged Memory Management Support"
319 Select if you want MMU-based virtualised addressing space
354 # This is sorted alphabetically by mach-* pathname. However, plat-*
[all …]
/linux/drivers/eisa/
H A Deisa.ids6 # Marc Zyngier <maz@wild-wind.fr.eu.org>
10 ABP0510 "Advansys ABP-510 ISA SCSI Host Adapter"
11 ABP0540 "Advansys ABP-540/542 ISA SCSI Host Adapter"
12 ABP7401 "AdvanSys ABP-740/742 EISA Single Channel SCSI Host Adapter"
13 ABP7501 "AdvanSys ABP-750/752 EISA Dual Channel SCSI Host Adapter"
14 ACC1200 "ACCTON EtherCombo-32 Ethernet Adapter"
15 ACC120A "ACCTON EtherCombo-32 Ethernet Adapter"
25 ACE7010 "ACME Multi-Function Board"
39 ACR1711 "AcerFrame 1000 486/33 SYSTEM-2"
41 ACR3211 "AcerFrame 3000MP 486 SYSTEM-1"
[all …]

1234