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/linux/arch/arm/common/
H A Dmcpm_head.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * arch/arm/common/mcpm_head.S -- kernel entry point for multi-cluster PM
6 * Copyright: (C) 2012-2013 Linaro Limited
8 * Refer to Documentation/arch/arm/cluster-pm-race-avoidance.rst
18 .arch armv7-a
28 1903: .asciz " cluster"
56 ubfx r10, r0, #8, #8 @ r10 = cluster
88 mla r8, r0, r10, r8 @ r8 = sync cluster base
96 @ At this point, the cluster cannot unexpectedly enter the GOING_DOWN
100 mla r11, r0, r10, r11 @ r11 = cluster first man lock
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H A Dmcpm_entry.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * arch/arm/common/mcpm_entry.c -- entry point for multi-cluster PM
6 * Copyright: (C) 2012-2013 Linaro Limited
24 * see Documentation/arch/arm/cluster-pm-race-avoidance.rst.
34 static void __mcpm_cpu_going_down(unsigned int cpu, unsigned int cluster) in __mcpm_cpu_going_down() argument
36 mcpm_sync.clusters[cluster].cpus[cpu].cpu = CPU_GOING_DOWN; in __mcpm_cpu_going_down()
37 sync_cache_w(&mcpm_sync.clusters[cluster].cpus[cpu].cpu); in __mcpm_cpu_going_down()
42 * cluster can be torn down without disrupting this CPU.
47 static void __mcpm_cpu_down(unsigned int cpu, unsigned int cluster) in __mcpm_cpu_down() argument
50 mcpm_sync.clusters[cluster].cpus[cpu].cpu = CPU_DOWN; in __mcpm_cpu_down()
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/linux/arch/mips/include/asm/
H A Dmips-cps.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
106 #include <asm/mips-cm.h>
107 #include <asm/mips-cpc.h>
108 #include <asm/mips-gic.h>
111 * mips_cps_numclusters - return the number of clusters present in the system
124 * mips_cps_cluster_config - return (GCR|CPC)_CONFIG from a cluster
125 * @cluster: the ID of the cluster whose config we want
127 * Read the value of GCR_CONFIG (or its CPC_CONFIG mirror) from a @cluster.
131 static inline uint64_t mips_cps_cluster_config(unsigned int cluster) in mips_cps_cluster_config() argument
139 * within this cluster. in mips_cps_cluster_config()
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/linux/Documentation/devicetree/bindings/cpu/
H A Dcpu-topology.txt6 1 - Introduction
12 - socket
13 - cluster
14 - core
15 - thread
18 symmetric multi-threading (SMT) is supported or not.
29 Currently, only ARM/RISC-V intend to use this cpu topology binding but it may be
39 2 - cpu-map node
42 The ARM/RISC-V CPU topology is defined within the cpu-map node, which is a direct
46 - cpu-map node
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/linux/arch/arm/mach-sunxi/
H A Dmc_smp.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2018 Chen-Yu Tsai
5 * Chen-Yu Tsai <wens@csie.org>
7 * arch/arm/mach-sunxi/mc_smp.c
9 * Based on Allwinner code, arch/arm/mach-exynos/mcpm-exynos.c, and
10 * arch/arm/mach-hisi/platmcpm.c
11 * Cluster cache enable trampoline code adapted from MCPM framework
14 #include <linux/arm-cci.h>
19 #include <linux/irqchip/arm-gic.h>
70 /* R_CPUCFG registers, specific to sun8i-a83t */
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/linux/drivers/gpu/drm/rockchip/
H A Drockchip_vop2_reg.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Author: Andy Yan <andy.yan@rock-chips.com>
29 DRM_FORMAT_YUV420_8BIT, /* yuv420_8bit non-Linear mode only */
30 DRM_FORMAT_YUV420_10BIT, /* yuv420_10bit non-Linear mode only */
31 DRM_FORMAT_YUYV, /* yuv422_8bit non-Linear mode only*/
32 DRM_FORMAT_Y210, /* yuv422_10bit non-Linear mode only */
159 * rk3568 vop with 2 cluster, 2 esmart win, 2 smart win.
160 * Every cluster can work as 4K win or split into two win.
161 * All win in cluster support AFBCD.
163 * Every esmart win and smart win support 4 Multi-region.
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/linux/Documentation/arch/arm/
H A Dcluster-pm-race-avoidance.rst2 Cluster-wide Power-up/power-down race avoidance algorithm
6 cluster setup and teardown operations and to manage hardware coherency
16 ---------
29 cluster-level operations are only performed when it is truly safe to do
34 are not immediately enabled when a cluster powers up. Since enabling or
35 disabling those mechanisms may itself be a non-atomic operation (such as
38 power-down and power-up at the cluster level.
46 -----------
48 Each cluster and CPU is assigned a state, as follows:
50 - DOWN
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/linux/arch/arm/mach-versatile/
H A Dspc.c1 // SPDX-License-Identifier: GPL-2.0-only
12 #include <linux/clk-provider.h>
28 #define SPCLOG "vexpress-spc: "
39 /* SPC wake-up IRQs status and mask */
46 /* SPC per-CPU mailboxes */
50 /* SPC CPU/cluster reset statue */
68 /* wake-up interrupt masks */
71 /* TC2 static dual-cluster configuration */
75 * Even though the SPC takes max 3-5 ms to complete any OPP/COMMS
97 * A15s cluster identifier
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H A Dplatsmp-vexpress.c1 // SPDX-License-Identifier: GPL-2.0-only
27 * The best way to detect a multi-cluster configuration in vexpress_smp_init_ops()
40 cci_node = of_parse_phandle(cpu_node, "cci-control-port", 0); in vexpress_smp_init_ops()
57 { .compatible = "arm,cortex-a5-scu", },
58 { .compatible = "arm,cortex-a9-scu", },
72 * system-wide flags register. The boot monitor waits in vexpress_smp_dt_prepare_cpus()
/linux/Documentation/admin-guide/perf/
H A Dhisi-pmu.rst10 The HiSilicon SoC encapsulates multiple CPU and IO dies. Each CPU cluster
12 called Super CPU cluster (SCCL) and is made up of 6 CCLs. Each SCCL has
13 two HHAs (0 - 1) and four DDRCs (0 - 3), respectively.
16 -------------------------------
27 name will appear in event listing as hisi_sccl<sccl-id>_module<index-id>.
28 where "sccl-id" is the identifier of the SCCL and "index-id" is the index of
44 ------------------------------------------
46 ------------------------------------------
48 ------------------------------------------
50 ------------------------------------------
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/linux/Documentation/devicetree/bindings/arm/
H A Darm,cci-400.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/arm/arm,cci-400.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
13 ARM multi-cluster systems maintain intra-cluster coherency through a cache
24 pattern: "^cci(@[0-9a-f]+)?$"
28 - arm,cci-400
29 - arm,cci-500
30 - arm,cci-550
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/linux/arch/mips/kernel/
H A Dmips-cm.c1 // SPDX-License-Identifier: GPL-2.0-or-later
11 #include <asm/mips-cps.h>
198 return (cmgcr & MIPS_CMGCRF_BASE) << (36 - 32); in mips_cm_phys_base()
206 * If the L2-only sync region is already enabled then leave it at it's in mips_cm_l2sync_phys_base()
222 /* L2-only sync was introduced with CM major revision 6 */ in mips_cm_probe_l2sync()
256 return -ENODEV; in mips_cm_probe()
260 return -ENXIO; in mips_cm_probe()
269 return -ENODEV; in mips_cm_probe()
285 /* probe for an L2-only sync region */ in mips_cm_probe()
297 void mips_cm_lock_other(unsigned int cluster, unsigned int core, in mips_cm_lock_other() argument
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/linux/fs/erofs/
H A Derofs_fs.h1 /* SPDX-License-Identifier: GPL-2.0-only OR Apache-2.0 */
3 * EROFS (Enhanced ROM File System) on-disk format definition
5 * Copyright (C) 2017-2018 HUAWEI, Inc.
54 /* erofs on-disk super block (currently 128 bytes) */
63 __le64 inos; /* total valid ino # (== f_files - f_favail) */
70 __u8 uuid[16]; /* 128-bit uuid for volume */
90 * EROFS inode datalayout (i_format in on-disk inode):
91 * 0 - uncompressed flat inode without tail-packing inline data:
92 * 1 - compressed inode with non-compact indexes:
93 * 2 - uncompressed flat inode with tail-packing inline data:
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/linux/fs/exfat/
H A Dexfat_fs.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright (C) 2012-2013 Samsung Electronics Co., Ltd.
52 (ES_IDX_FIRST_FILENAME + EXFAT_FILENAME_ENTRY_NUM(name_len) - 1)
78 #define MAX_CHARSET_SIZE 6 /* max size of multi-byte character */
82 #define EXFAT_HINT_NONE -1
86 * helpers for cluster size to byte conversion.
88 #define EXFAT_CLU_TO_B(b, sbi) ((b) << (sbi)->cluster_size_bits)
89 #define EXFAT_B_TO_CLU(b, sbi) ((b) >> (sbi)->cluster_size_bits)
91 (((b - 1) >> (sbi)->cluster_size_bits) + 1)
92 #define EXFAT_CLU_OFFSET(off, sbi) ((off) & ((sbi)->cluster_size - 1))
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/linux/drivers/bus/
H A Darm-cci.c17 #include <linux/arm-cci.h>
49 {.compatible = "arm,cci-400", .data = CCI400_PORTS_DATA },
52 { .compatible = "arm,cci-500", },
53 { .compatible = "arm,cci-550", },
59 OF_DEV_AUXDATA("arm,cci-400-pmu", 0, NULL, &cci_ctrl_base),
60 OF_DEV_AUXDATA("arm,cci-400-pmu,r0", 0, NULL, &cci_ctrl_base),
61 OF_DEV_AUXDATA("arm,cci-400-pmu,r1", 0, NULL, &cci_ctrl_base),
62 OF_DEV_AUXDATA("arm,cci-500-pmu,r0", 0, NULL, &cci_ctrl_base),
63 OF_DEV_AUXDATA("arm,cci-550-pmu,r0", 0, NULL, &cci_ctrl_base),
67 #define DRIVER_NAME "ARM-CCI"
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/linux/Documentation/devicetree/bindings/soc/qcom/
H A Dqcom,saw2.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andy Gross <agross@kernel.org>
11 - Bjorn Andersson <bjorn.andersson@linaro.org>
19 power-controller that transitions a piece of hardware (like a processor or
27 - enum:
28 - qcom,ipq4019-saw2-cpu
29 - qcom,ipq4019-saw2-l2
30 - qcom,ipq8064-saw2-cpu
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/linux/drivers/acpi/
H A Dpptt.c1 // SPDX-License-Identifier: GPL-2.0
3 * pptt.c - parsing of Processor Properties Topology Table (PPTT)
33 if (pptt_ref + sizeof(struct acpi_subtable_header) > table_hdr->length) in fetch_pptt_subtable()
38 if (entry->length == 0) in fetch_pptt_subtable()
41 if (pptt_ref + entry->length > table_hdr->length) in fetch_pptt_subtable()
65 if (resource >= node->number_of_priv_resources) in acpi_get_pptt_resource()
81 * acpi_pptt_walk_cache() - Attempt to find the requested acpi_pptt_cache
111 if (res->type != ACPI_PPTT_TYPE_CACHE) in acpi_pptt_walk_cache()
118 if (!(cache->flags & ACPI_PPTT_CACHE_TYPE_VALID)) { in acpi_pptt_walk_cache()
119 cache = fetch_pptt_cache(table_hdr, cache->next_level_of_cache); in acpi_pptt_walk_cache()
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/linux/drivers/media/v4l2-core/
H A Dv4l2-ctrls-api.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (C) 2010-2021 Hans Verkuil <hverkuil-cisco@xs4all.nl>
8 #define pr_fmt(fmt) "v4l2-ctrls: " fmt
13 #include <media/v4l2-ctrls.h>
14 #include <media/v4l2-dev.h>
15 #include <media/v4l2-device.h>
16 #include <media/v4l2-event.h>
17 #include <media/v4l2-ioctl.h>
19 #include "v4l2-ctrls-priv.h"
29 * same cluster, or 0 if there isn't any.
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/linux/arch/arm/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
159 The ARM series is a line of low-power-consumption RISC chip designs
161 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
162 manufactured, but legacy ARM-based PC hardware remains popular in
173 supported in LLD until version 14. The combined range is -/+ 256 MiB,
266 Patch phys-to-virt and virt-to-phys translation functions at
270 This can only be used with non-XIP MMU kernels where the base
316 bool "MMU-based Paged Memory Management Support"
319 Select if you want MMU-based virtualised addressing space
354 # This is sorted alphabetically by mach-* pathname. However, plat-*
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/linux/Documentation/arch/arm/samsung/
H A Dbootloader-interface.rst14 In the document "boot loader" means any of following: U-boot, proprietary
19 1. Non-Secure mode
65 3. Other (regardless of secure/non-secure mode)
72 0x0908 Non-zero Secondary CPU boot up indicator
79 AFTR - ARM Off Top Running, a low power mode, Cortex cores and many other
81 MCPM - Multi-Cluster Power Management
/linux/fs/dlm/
H A Dlowcomms.c1 // SPDX-License-Identifier: GPL-2.0-only
5 ** Copyright (C) Sistina Software, Inc. 1997-2003 All rights reserved.
6 ** Copyright (C) 2004-2009 Red Hat, Inc. All rights reserved.
15 * This is the "low-level" comms layer.
18 * from other nodes in the cluster.
20 * Cluster nodes are referred to by their nodeids. nodeids are
21 * simply 32 bit numbers to the locking module - if they need to
22 * be expanded for the cluster infrastructure then that is its
25 * whatever it needs for inter-node communication.
29 * up to the mid-level comms layer (which understands the
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/linux/drivers/edac/
H A Dx38_edac.c3 * Copyright (C) 2008 Cluster Computing, Inc.
18 #include <linux/io-64-nonatomic-lo-hi.h>
29 /* Intel X38 register addresses - device 0 function 0 - DRAM Controller */
55 * 9 LOCK to non-DRAM Memory Flag (LCKF)
59 * 1 Multi-bit DRAM ECC Error Flag (DMERR)
60 * 0 Single-bit DRAM ECC Error Flag (DSERR)
67 /* Intel MMIO register space - device 0 function 0 - MMR space */
154 pdev = to_pci_dev(mci->pdev); in x38_clear_error_info()
168 void __iomem *window = mci->pvt_info; in x38_get_and_clear_error_info()
170 pdev = to_pci_dev(mci->pdev); in x38_get_and_clear_error_info()
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/linux/drivers/media/dvb-frontends/
H A Dnxt200x.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Support for NXT2002 and NXT2004 - VSB/QAM
6 * Copyright (C) 2006-2014 Michael Krufky <mkrufky@linuxtv.org>
8 * and nxt2004 by Jean-Francois Thibert <jeanfrancois@sagetv.com>
15 * B2C2/BBTI Technisat Air2PC - ATSC (NXT2002)
31 #define NXT2002_DEFAULT_FIRMWARE "dvb-fe-nxt2002.fw"
32 #define NXT2004_DEFAULT_FIRMWARE "dvb-fe-nxt2004.fw"
63 if ((err = i2c_transfer (state->i2c, &msg, 1)) != 1) { in i2c_writebytes()
66 return -EREMOTEIO; in i2c_writebytes()
76 if ((err = i2c_transfer (state->i2c, &msg, 1)) != 1) { in i2c_readbytes()
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/linux/mm/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
33 compress them into a dynamically allocated RAM-based memory pool.
189 linux-mm@kvack.org and the zswap maintainers.
207 zsmalloc is a slab-based memory allocator designed to store
222 int "Maximum number of physical pages per-zspage"
295 specifically-sized allocations with user-controlled contents
299 user-controlled allocations. This may very slightly increase
301 of extra pages since the bulk of user-controlled allocations
302 are relatively long-lived.
317 Try running: slabinfo -DA
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/linux/arch/arm64/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
275 ARM 64-bit (AArch64) Linux support.
283 # required due to use of the -Zfixed-x18 flag.
286 # -Zsanitizer=shadow-call-stack flag.
296 depends on $(cc-option,-fpatchable-function-entry=2)
322 # VA_BITS - PAGE_SHIFT - 3
400 def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n)
405 # https://github.com/llvm/llvm-project/commit/2a96f47c5ffca84cd774ad402cacd137f4bf45e2
455 at stage-2.
463 …bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is acce…
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