Searched +full:mt8173 +full:- +full:dpi (Results 1 – 11 of 11) sorted by relevance
/linux/Documentation/devicetree/bindings/display/mediatek/ |
H A D | mediatek,dpi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/display/mediatek/mediatek,dpi.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: MediaTek DPI and DP_INTF Controller 10 - CK Hu <ck.hu@mediatek.com> 11 - Jitao shi <jitao.shi@mediatek.com> 14 The MediaTek DPI and DP_INTF function blocks are a sink of the display 15 subsystem and provides 8-bit RGB/YUV444 or 8/10/10-bit YUV422 pixel data on a 21 - enum: [all …]
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H A D | mediatek,hdmi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - CK Hu <ck.hu@mediatek.com> 11 - Jitao shi <jitao.shi@mediatek.com> 20 - mediatek,mt2701-hdmi 21 - mediatek,mt7623-hdmi 22 - mediatek,mt8167-hdmi 23 - mediatek,mt8173-hdmi 33 - description: Pixel Clock [all …]
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/linux/drivers/gpu/drm/mediatek/ |
H A D | mtk_drm_drv.c | 1 // SPDX-License-Identifier: GPL-2.0-only 13 #include <linux/dma-mapping.h> 50 if (info->num_planes != 1) in mtk_drm_mode_fb_create() 51 return ERR_PTR(-EINVAL); in mtk_drm_mode_fb_create() 326 .min_width = 2, /* 2-pixel align when ethdr is bypassed */ 331 { .compatible = "mediatek,mt2701-mmsys", 333 { .compatible = "mediatek,mt7623-mmsys", 335 { .compatible = "mediatek,mt2712-mmsys", 337 { .compatible = "mediatek,mt8167-mmsys", 339 { .compatible = "mediatek,mt8173-mmsys", [all …]
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H A D | mtk_dpi.c | 1 // SPDX-License-Identifier: GPL-2.0-only 11 #include <linux/media-bus-format.h> 16 #include <linux/soc/mediatek/mtk-mmsys.h> 120 * struct mtk_dpi_conf - Configuration of mediatek dpi. 129 * @support_direct_pin: IP supports direct connection to dpi panels. 139 * @edge_cfg_in_mmsys: If the edge configuration for DPI's output needs to be set in MMSYS. 161 static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32 mask) in mtk_dpi_mask() argument 163 u32 tmp = readl(dpi->regs + offset) & ~mask; in mtk_dpi_mask() 166 writel(tmp, dpi->regs + offset); in mtk_dpi_mask() 169 static void mtk_dpi_sw_reset(struct mtk_dpi *dpi, bool reset) in mtk_dpi_sw_reset() argument [all …]
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H A D | mtk_disp_rdma.c | 1 // SPDX-License-Identifier: GPL-2.0-only 14 #include <linux/soc/mediatek/mtk-cmdq.h> 52 #define RDMA_FIFO_SIZE(rdma) ((rdma)->data->fifo_size) 78 * struct mtk_disp_rdma - DISP_RDMA driver structure 96 writel(0x0, priv->regs + DISP_REG_RDMA_INT_STATUS); in mtk_disp_rdma_irq_handler() 98 if (!priv->vblank_cb) in mtk_disp_rdma_irq_handler() 101 priv->vblank_cb(priv->vblank_cb_data); in mtk_disp_rdma_irq_handler() 110 unsigned int tmp = readl(rdma->regs + reg); in rdma_update_bits() 113 writel(tmp, rdma->regs + reg); in rdma_update_bits() 122 rdma->vblank_cb = vblank_cb; in mtk_rdma_register_vblank_cb() [all …]
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H A D | mtk_hdmi.c | 1 // SPDX-License-Identifier: GPL-2.0-only 7 #include <linux/arm-smccc.h> 24 #include <sound/hdmi-codec.h> 192 return readl(hdmi->regs + offset); in mtk_hdmi_read() 197 writel(val, hdmi->regs + offset); in mtk_hdmi_write() 202 void __iomem *reg = hdmi->regs + offset; in mtk_hdmi_clear_bits() 212 void __iomem *reg = hdmi->regs + offset; in mtk_hdmi_set_bits() 222 void __iomem *reg = hdmi->regs + offset; in mtk_hdmi_mask() 241 * MT8173 HDMI hardware has an output control bit to enable/disable HDMI in mtk_hdmi_hw_make_reg_writable() 246 if (hdmi->conf && hdmi->conf->tz_disabled) in mtk_hdmi_hw_make_reg_writable() [all …]
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/linux/arch/arm64/boot/dts/mediatek/ |
H A D | mt6795.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only 9 #include <dt-bindings/interrupt-controller/irq.h> 10 #include <dt-bindings/interrupt-controller/arm-gic.h> 11 #include <dt-bindings/clock/mediatek,mt6795-clk.h> 12 #include <dt-bindings/gce/mediatek,mt6795-gce.h> 13 #include <dt-bindings/memory/mt6795-larb-port.h> 14 #include <dt-bindings/pinctrl/mt6795-pinfunc.h> 15 #include <dt-bindings/power/mt6795-power.h> 16 #include <dt-bindings/reset/mediatek,mt6795-resets.h> 20 interrupt-parent = <&sysirq>; [all …]
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H A D | mt8173.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only 7 #include <dt-bindings/clock/mt8173-clk.h> 8 #include <dt-bindings/interrupt-controller/irq.h> 9 #include <dt-bindings/interrupt-controller/arm-gic.h> 10 #include <dt-bindings/memory/mt8173-larb-port.h> 11 #include <dt-bindings/phy/phy.h> 12 #include <dt-bindings/power/mt8173-power.h> 13 #include <dt-bindings/reset/mt8173-resets.h> 14 #include <dt-bindings/gce/mt8173-gce.h> 15 #include <dt-bindings/thermal/thermal.h> [all …]
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H A D | mt8192.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 7 /dts-v1/; 8 #include <dt-bindings/clock/mt8192-clk.h> 9 #include <dt-bindings/gce/mt8192-gce.h> 10 #include <dt-bindings/interrupt-controller/arm-gic.h> 11 #include <dt-bindings/interrupt-controller/irq.h> 12 #include <dt-bindings/memory/mt8192-larb-port.h> 13 #include <dt-bindings/pinctrl/mt8192-pinfunc.h> 14 #include <dt-bindings/phy/phy.h> 15 #include <dt-bindings/power/mt8192-power.h> [all …]
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/linux/arch/arm/boot/dts/mediatek/ |
H A D | mt7623n.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 3 * Copyright © 2017-2020 MediaTek Inc. 10 #include <dt-bindings/memory/mt2701-larb-port.h> 19 compatible = "mediatek,mt7623-g3dsys", 20 "mediatek,mt2701-g3dsys", 23 #clock-cells = <1>; 24 #reset-cells = <1>; 28 compatible = "mediatek,mt7623-mali", "arm,mali-450"; 41 interrupt-names = "gp", "gpmmu", "pp0", "ppmmu0", "pp1", 46 clock-names = "bus", "core"; [all …]
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/linux/drivers/clk/mediatek/ |
H A D | clk-mt8173-topckgen.c | 1 // SPDX-License-Identifier: GPL-2.0-only 8 #include <dt-bindings/clock/mt8173-clk.h> 11 #include "clk-gate.h" 12 #include "clk-mtk.h" 13 #include "clk-mux.h" 25 _gate, 0, -1, _flags) 575 * clock so the dpi driver can have full control over PLL and divider. 638 { .compatible = "mediatek,mt8173-topckgen", .data = &topck_desc }, 645 .name = "clk-mt8173-topckgen", 653 MODULE_DESCRIPTION("MediaTek MT8173 topckgen clocks driver");
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