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/linux/Documentation/devicetree/bindings/serial/
H A Dqcom,msm-uart.yaml1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/serial/qcom,msm-uart.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm MSM SoC Serial UART
10 - Bjorn Andersson <andersson@kernel.org>
11 - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
14 The MSM serial UART hardware is designed for low-speed use cases where a
15 dma-engine isn't needed. From a software perspective it's mostly compatible
16 with the MSM serial UARTDM except that it only supports reading and writing
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H A Dqcom,msm-uartdm.yaml1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/serial/qcom,msm-uartdm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm MSM Serial UARTDM
10 - Andy Gross <agross@kernel.org>
11 - Bjorn Andersson <bjorn.andersson@linaro.org>
12 - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
15 The MSM serial UARTDM hardware is designed for high-speed use cases where the
16 transmit and/or receive channels can be offloaded to a dma-engine. From a
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/linux/Documentation/devicetree/bindings/soc/qcom/
H A Dqcom,gsbi.yaml1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andy Gross <agross@kernel.org>
11 - Bjorn Andersson <bjorn.andersson@linaro.org>
12 - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
16 representing a serial sub-node device that is mux'd as part of the GSBI
21 devices. These serial devices can be a QCOM UART, I2C controller, spi
26 const: qcom,gsbi-v1.0.0
28 '#address-cells':
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/linux/drivers/tty/serial/
H A Dmsm_serial.c1 // SPDX-License-Identifier: GPL-2.0
13 #include <linux/dma-mapping.h>
178 struct uart_port uart; member
192 return container_of(up, struct msm_port, uart); in to_msm_port()
198 writel_relaxed(val, port->membase + off); in msm_write()
204 return readl_relaxed(port->membase + off); in msm_read()
216 port->uartclk = 1843200; in msm_serial_set_mnd_regs_tcxo()
228 port->uartclk = 1843200; in msm_serial_set_mnd_regs_tcxoby4()
239 if (msm_port->is_uartdm) in msm_serial_set_mnd_regs()
242 if (port->uartclk == 19200000) in msm_serial_set_mnd_regs()
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H A Dqcom_geni_serial.c1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2017-2018, The Linux foundation. All rights reserved.
18 #include <linux/soc/qcom/geni-se.h>
24 #include <dt-bindings/interconnect/qcom,icc.h>
26 /* UART specific GENI registers */
68 /* UART M_CMD OP codes */
70 /* UART S_CMD OP codes */
90 /* UART pin swap value */
195 struct platform_device *pdev = to_platform_device(uport->dev); in qcom_geni_serial_request_port()
198 uport->membase = devm_platform_ioremap_resource(pdev, 0); in qcom_geni_serial_request_port()
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/linux/include/uapi/linux/
H A Dserial_core.h1 /* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
19 #define PORT_RM9000 16 /* PMC-Sierra RM9xxx internal UART */
20 #define PORT_OCTEON 17 /* Cavium OCTEON internal UART */
21 #define PORT_AR7 18 /* Texas Instruments AR7 internal UART */
22 #define PORT_U6_16550A 19 /* ST-Ericsson U6xxx internal UART */
23 #define PORT_TEGRA 20 /* NVIDIA Tegra internal UART */
24 #define PORT_XR17D15X 21 /* Exar XR17D15x UART */
25 #define PORT_LPC3220 22 /* NXP LPC32xx SoC "Standard" UART */
29 #define PORT_ALTR_16550_F32 26 /* Altera 16550 UART with 32 FIFOs */
30 #define PORT_ALTR_16550_F64 27 /* Altera 16550 UART with 64 FIFOs */
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/linux/arch/arm64/boot/dts/qcom/
H A Dmsm8953.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
4 #include <dt-bindings/clock/qcom,gcc-msm8953.h>
5 #include <dt-bindings/clock/qcom,rpmcc.h>
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/power/qcom-rpmpd.h>
9 #include <dt-bindings/soc/qcom,apr.h>
10 #include <dt-bindings/sound/qcom,q6afe.h>
11 #include <dt-bindings/sound/qcom,q6asm.h>
12 #include <dt-bindings/thermal/thermal.h>
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H A Dapq8016-schneider-hmibsc.dts1 // SPDX-License-Identifier: GPL-2.0-only
7 /dts-v1/;
9 #include "msm8916-pm8916.dtsi"
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/input/input.h>
12 #include <dt-bindings/leds/common.h>
13 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
14 #include <dt-bindings/pinctrl/qcom,pmic-mpp.h>
15 #include <dt-bindings/sound/apq8016-lpass.h>
19 compatible = "schneider,apq8016-hmibsc", "qcom,apq8016";
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H A Dapq8016-sbc.dts1 // SPDX-License-Identifier: GPL-2.0-only
6 /dts-v1/;
8 #include "msm8916-pm8916.dtsi"
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/leds/common.h>
12 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
13 #include <dt-bindings/pinctrl/qcom,pmic-mpp.h>
14 #include <dt-bindings/sound/apq8016-lpass.h>
18 compatible = "qcom,apq8016-sbc", "qcom,apq8016";
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H A Dqcm2290.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
8 #include <dt-bindings/clock/qcom,dispcc-qcm2290.h>
9 #include <dt-bindings/clock/qcom,gcc-qcm2290.h>
10 #include <dt-bindings/clock/qcom,qcm2290-gpucc.h>
11 #include <dt-bindings/clock/qcom,rpmcc.h>
12 #include <dt-bindings/dma/qcom-gpi.h>
13 #include <dt-bindings/firmware/qcom,scm.h>
14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 #include <dt-bindings/interconnect/qcom,qcm2290.h>
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H A Dx1e80100.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/clock/qcom,rpmh.h>
7 #include <dt-bindings/clock/qcom,sc8280xp-lpasscc.h>
8 #include <dt-bindings/clock/qcom,x1e80100-dispcc.h>
9 #include <dt-bindings/clock/qcom,x1e80100-gcc.h>
10 #include <dt-bindings/clock/qcom,x1e80100-gpucc.h>
11 #include <dt-bindings/clock/qcom,x1e80100-tcsr.h>
12 #include <dt-bindings/dma/qcom-gpi.h>
13 #include <dt-bindings/interconnect/qcom,icc.h>
14 #include <dt-bindings/interconnect/qcom,x1e80100-rpmh.h>
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/linux/
H A DMAINTAINERS5 ---------------------------------------------------
21 W: *Web-page* with status/info
23 B: URI for where to file *bugs*. A web-page with detailed bug
28 patches to the given subsystem. This is either an in-tree file,
29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst
46 N: [^a-z]tegra all files whose path contains tegra
64 ----------------
83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS)
85 L: linux-scsi@vger.kernel.org
88 F: drivers/scsi/3w-*
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/linux/Documentation/admin-guide/
H A Dkernel-parameters.txt16 force -- enable ACPI if default was off
17 on -- enable ACPI but allow fallback to DT [arm64,riscv64]
18 off -- disable ACPI if default was on
19 noirq -- do not use ACPI for IRQ routing
20 strict -- Be less tolerant of platforms that are not
22 rsdt -- prefer RSDT over (default) XSDT
23 copy_dsdt -- copy DSDT to memory
24 nocmcff -- Disable firmware first mode for corrected
28 nospcr -- disable console in ACPI SPCR table as
45 If set to vendor, prefer vendor-specific driver
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