Home
last modified time | relevance | path

Searched +full:msm +full:- +full:uart (Results 1 – 25 of 43) sorted by relevance

12

/freebsd/sys/contrib/device-tree/Bindings/serial/
H A Dqcom,msm-uartdm.txt1 * MSM Serial UARTDM
3 The MSM serial UARTDM hardware is designed for high-speed use cases where the
4 transmit and/or receive channels can be offloaded to a dma-engine. From a
5 software perspective it's mostly compatible with the MSM serial UART except
9 - compatible: Should contain at least "qcom,msm-uartdm".
12 "qcom,msm-uartdm-v1.1"
13 "qcom,msm-uartdm-v1.2"
14 "qcom,msm-uartdm-v1.3"
15 "qcom,msm-uartdm-v1.4"
16 - reg: Should contain UART register locations and lengths. The first
[all …]
H A Dqcom,msm-uart.txt1 * MSM Serial UART
3 The MSM serial UART hardware is designed for low-speed use cases where a
4 dma-engine isn't needed. From a software perspective it's mostly compatible
5 with the MSM serial UARTDM except that it only supports reading and writing one
9 - compatible: Should contain "qcom,msm-uart"
10 - reg: Should contain UART register location and length.
11 - interrupts: Should contain UART interrupt.
12 - clocks: Should contain the core clock.
13 - clock-names: Should be "core".
17 A uart device at 0xa9c00000 with interrupt 11.
[all …]
H A Dqcom,msm-uart.yaml1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/serial/qcom,msm-uar
[all...]
H A Dqcom,msm-uartdm.yaml1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/serial/qcom,msm-uartd
[all...]
/freebsd/sys/contrib/device-tree/Bindings/soc/qcom/
H A Dqcom,gsbi.yaml1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andy Gross <agross@kernel.org>
11 - Bjorn Andersson <bjorn.andersson@linaro.org>
12 - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
16 representing a serial sub-node device that is mux'd as part of the GSBI
21 devices. These serial devices can be a QCOM UART, I2C controller, spi
26 const: qcom,gsbi-v1.0.0
28 '#address-cells':
[all …]
H A Dqcom,gsbi.txt4 representing a serial sub-node device that is mux'd as part of the GSBI
9 - compatible: Should contain "qcom,gsbi-v1.0.0"
10 - cell-index: Should contain the GSBI index
11 - reg: Address range for GSBI registers
12 - clocks: required clock
13 - clock-names: must contain "iface" entry
14 - qcom,mode : indicates MUX value for configuration of the serial interface.
15 Please reference dt-bindings/soc/qcom,gsbi.h for valid mux values.
18 - qcom,crci : indicates CRCI MUX value for QUP CRCI ports. Please reference
19 dt-bindings/soc/qcom,gsbi.h for valid CRCI mux values.
[all …]
/freebsd/sys/dev/uart/
H A Duart_dev_msm.c1 /*-
27 /* Qualcomm MSM7K/8K uart driver */
39 #include <dev/uart/uart.h>
40 #include <dev/uart/uart_cpu.h>
41 #include <dev/uart/uart_cpu_fdt.h>
42 #include <dev/uart/uart_bus.h>
43 #include <dev/uart/uart_dev_msm.h>
50 bus_space_read_4((bas)->bst, (bas)->bsh, (reg))
52 bus_space_write_4((bas)->bst, (bas)->bsh, (reg), (value))
57 * Low-level UART interface.
[all …]
/freebsd/sys/contrib/device-tree/Bindings/dma/
H A Dqcom_bam_dma.txt4 - compatible: must be one of the following:
5 * "qcom,bam-v1.4.0" for MSM8974, APQ8074 and APQ8084
6 * "qcom,bam-v1.3.0" for APQ8064, IPQ8064 and MSM8960
7 * "qcom,bam-v1.7.0" for MSM8916
8 - reg: Address range for DMA registers
9 - interrupts: Should contain the one interrupt shared by all channels
10 - #dma-cells: must be <1>, the cell in the dmas property of the client device
12 - clocks: required clock
13 - clock-names: must contain "bam_clk" entry
14 - qcom,ee : indicates the active Execution Environment identifier (0-7) used in
[all …]
/freebsd/sys/arm/conf/
H A Dstd.qca7 makeoptions CONF_CFLAGS="-march=armv7a"
12 device uart
13 device uart_msm # Qualcomm MSM UART driver
45 # PSCI - SMC calls, needed for qualcomm SCM
/freebsd/sys/arm64/conf/
H A DNOTES2 # NOTES -- Lines that can be cut/pasted into kernel and hints configs.
25 makeoptions DEBUG=-g # Build kernel with gdb(1) debug symbols
30 options VFP # Floating-point support
69 # Microsoft Hyper-V
80 device al_pci # Annapurna Alpine PCI-E
81 options PCI_HP # PCI-Express native HotPlug
82 options PCI_IOV # PCI SR-IOV support
102 # Broadcom MPT Fusion, version 4, is 64-bit only
103 device mpi3mr # LSI-Logic MPT-Fusion 4
113 device uart_msm # Qualcomm MSM UART driver
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/qcom/
H A Dmsm8953.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
4 #include <dt-bindings/clock/qcom,gcc-msm8953.h>
5 #include <dt-bindings/clock/qcom,rpmcc.h>
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/power/qcom-rpmpd.h>
9 #include <dt-bindings/soc/qcom,apr.h>
10 #include <dt-bindings/sound/qcom,q6afe.h>
11 #include <dt-bindings/sound/qcom,q6asm.h>
12 #include <dt-bindings/thermal/thermal.h>
[all …]
H A Dsdm845.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/clock/qcom,camcc-sdm845.h>
9 #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
10 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
11 #include <dt-bindings/clock/qcom,gpucc-sdm845.h>
12 #include <dt-bindings/clock/qcom,lpass-sdm845.h>
13 #include <dt-bindings/clock/qcom,rpmh.h>
14 #include <dt-bindings/clock/qcom,videocc-sdm845.h>
15 #include <dt-bindings/dma/qcom-gpi.h>
16 #include <dt-bindings/firmware/qcom,scm.h>
[all …]
H A Dsc7180.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
5 * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
8 #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
9 #include <dt-bindings/clock/qcom,gcc-sc7180.h>
10 #include <dt-bindings/clock/qcom,gpucc-sc7180.h>
11 #include <dt-bindings/clock/qcom,lpasscorecc-sc7180.h>
12 #include <dt-bindings/clock/qcom,rpmh.h>
13 #include <dt-bindings/clock/qcom,videocc-sc7180.h>
14 #include <dt-bindings/firmware/qcom,scm.h>
15 #include <dt-bindings/interconnect/qcom,icc.h>
[all …]
H A Dapq8016-schneider-hmibsc.dts1 // SPDX-License-Identifier: GPL-2.0-only
7 /dts-v1/;
9 #include "msm8916-pm8916.dtsi"
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/input/input.h>
12 #include <dt-bindings/leds/common.h>
13 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
14 #include <dt-bindings/pinctrl/qcom,pmic-mpp.h>
15 #include <dt-bindings/sound/apq8016-lpass.h>
19 compatible = "schneider,apq8016-hmibsc", "qcom,apq8016";
[all …]
H A Dsc7280.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
5 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
7 #include <dt-bindings/clock/qcom,camcc-sc7280.h>
8 #include <dt-bindings/clock/qcom,dispcc-sc7280.h>
9 #include <dt-bindings/clock/qcom,gcc-sc7280.h>
10 #include <dt-bindings/clock/qcom,gpucc-sc7280.h>
11 #include <dt-bindings/clock/qcom,lpassaudiocc-sc7280.h>
12 #include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h>
13 #include <dt-bindings/clock/qcom,rpmh.h>
14 #include <dt-bindings/clock/qcom,videocc-sc7280.h>
[all …]
H A Dapq8016-sbc.dts1 // SPDX-License-Identifier: GPL-2.0-only
6 /dts-v1/;
8 #include "msm8916-pm8916.dtsi"
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/leds/common.h>
12 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
13 #include <dt-bindings/pinctrl/qcom,pmic-mpp.h>
14 #include <dt-bindings/sound/apq8016-lpass.h>
18 compatible = "qcom,apq8016-sbc", "qcom,apq8016";
[all …]
H A Dapq8016-sbc.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
6 #include "msm8916-pm8916.dtsi"
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/input/input.h>
9 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
10 #include <dt-bindings/pinctrl/qcom,pmic-mpp.h>
11 #include <dt-bindings/sound/apq8016-lpass.h>
26 stdout-path = "serial0";
29 camera_vdddo_1v8: camera-vdddo-1v8 {
30 compatible = "regulator-fixed";
[all …]
H A Dsdx75.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
9 #include <dt-bindings/clock/qcom,rpmh.h>
10 #include <dt-bindings/clock/qcom,sdx75-gcc.h>
11 #include <dt-bindings/dma/qcom-gpi.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/interconnect/qcom,icc.h>
14 #include <dt-bindings/interconnect/qcom,sdx75.h>
15 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 #include <dt-bindings/mailbox/qcom-ipcc.h>
17 #include <dt-bindings/power/qcom,rpmhpd.h>
[all …]
H A Dqdu1000.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/clock/qcom,qdu1000-gcc.h>
7 #include <dt-bindings/clock/qcom,rpmh.h>
8 #include <dt-bindings/dma/qcom-gpi.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interconnect/qcom,icc.h>
11 #include <dt-bindings/interconnect/qcom,qdu1000-rpmh.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/power/qcom-rpmpd.h>
14 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
[all …]
H A Dsm8350.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/interconnect/qcom,sm8350.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/clock/qcom,dispcc-sm8350.h>
9 #include <dt-bindings/clock/qcom,gcc-sm8350.h>
10 #include <dt-bindings/clock/qcom,gpucc-sm8350.h>
11 #include <dt-bindings/clock/qcom,rpmh.h>
12 #include <dt-bindings/dma/qcom-gpi.h>
13 #include <dt-bindings/firmware/qcom,scm.h>
14 #include <dt-bindings/gpio/gpio.h>
[all …]
H A Dqcm2290.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
8 #include <dt-bindings/clock/qcom,dispcc-qcm2290.h>
9 #include <dt-bindings/clock/qcom,gcc-qcm2290.h>
10 #include <dt-bindings/clock/qcom,qcm2290-gpucc.h>
11 #include <dt-bindings/clock/qcom,rpmcc.h>
12 #include <dt-bindings/dma/qcom-gpi.h>
13 #include <dt-bindings/firmware/qcom,scm.h>
14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 #include <dt-bindings/interconnect/qcom,qcm2290.h>
[all …]
/illumos-gate/usr/src/uts/common/io/qede/579xx/hsi/hw/
H A Dreg_addr_bb.h9 * or http://opensource.org/licenses/CDDL-1.0.
23 * Copyright 2014-2017 Cavium, Inc.
30 * at http://opensource.org/licenses/CDDL-1.0
84 …- For ending "endless completion". 0 - When receiving a completion timeout while receiving a compl…
85 … DataWidth:0x4 // 0 - TXCPL sync fifo pop underflow 1 - TXR sync fifo pop underflow 2 - TXW hea…
86 …s:R DataWidth:0x6 // 0 - RX target read and config sync fifo push overflow 1 - RX header syn…
87 …ataWidth:0x14 // 4:0 - TXCPL sync fifo pop status 9:5 - TXR sync fifo pop status 14:10 - TXW hea…
89 …ffff<<0) // Vendor ID. PCI-SIG assigned Manufacturer Identifier. Note: The access attributes of …
91 …ce Identifier. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
99 …l has_io_bar=0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
[all …]
H A Dreg_addr_k2.h9 * or http://opensource.org/licenses/CDDL-1.0.
23 * Copyright 2014-2017 Cavium, Inc.
30 * at http://opensource.org/licenses/CDDL-1.0
84 …- For ending "endless completion". 0 - When receiving a completion timeout while receiving a compl…
85 … DataWidth:0x4 // 0 - TXCPL sync fifo pop underflow 1 - TXR sync fifo pop underflow 2 - TXW hea…
86 …s:R DataWidth:0x6 // 0 - RX target read and config sync fifo push overflow 1 - RX header syn…
87 …ataWidth:0x14 // 4:0 - TXCPL sync fifo pop status 9:5 - TXR sync fifo pop status 14:10 - TXW hea…
89 …ffff<<0) // Vendor ID. PCI-SIG assigned Manufacturer Identifier. Note: The access attributes of …
91 …ce Identifier. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
99 …l has_io_bar=0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
[all …]
H A Dreg_addr_e5.h9 * or http://opensource.org/licenses/CDDL-1.0.
23 * Copyright 2014-2017 Cavium, Inc.
30 * at http://opensource.org/licenses/CDDL-1.0
84 …- For ending "endless completion". 0 - When receiving a completion timeout while receiving a compl…
85 … DataWidth:0x4 // 0 - TXCPL sync fifo pop underflow 1 - TXR sync fifo pop underflow 2 - TXW hea…
86 …s:R DataWidth:0x6 // 0 - RX target read and config sync fifo push overflow 1 - RX header syn…
87 …ataWidth:0x14 // 4:0 - TXCPL sync fifo pop status 9:5 - TXR sync fifo pop status 14:10 - TXW hea…
89 …ffff<<0) // Vendor ID. PCI-SIG assigned Manufacturer Identifier. Note: The access attributes of …
91 …ce Identifier. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
99 …l has_io_bar=0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
[all …]
H A Dreg_addr_ah_compile15.h9 * or http://opensource.org/licenses/CDDL-1.0.
23 * Copyright 2014-2017 Cavium, Inc.
30 * at http://opensource.org/licenses/CDDL-1.0
85 …ffff<<0) // Vendor ID. PCI-SIG assigned Manufacturer Identifier. Note: The access attributes of …
87 …ce Identifier. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
96 …l has_io_bar=0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
98 … has_mem_bar=0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
144 …_SYS_ERR (0x1<<30) // Fatal or Non-Fatal Error Message s…
148 …:0x20 This is the PCIE compliant status/command register (bits 31-16: status, bits 15-0: command)…
149 …:0x20 This is the PCIE compliant status/command register (bits 31-16: status, bits 15-0: command)…
[all …]

12