Lines Matching +full:msm +full:- +full:uart

1 * MSM Serial UARTDM
3 The MSM serial UARTDM hardware is designed for high-speed use cases where the
4 transmit and/or receive channels can be offloaded to a dma-engine. From a
5 software perspective it's mostly compatible with the MSM serial UART except
9 - compatible: Should contain at least "qcom,msm-uartdm".
12 		"qcom,msm-uartdm-v1.1"
13 		"qcom,msm-uartdm-v1.2"
14 		"qcom,msm-uartdm-v1.3"
15 		"qcom,msm-uartdm-v1.4"
16 - reg: Should contain UART register locations and lengths. The first
19        "qcom,msm-uartdm-v1.3" is the only compatible value that might
21 - interrupts: Should contain UART interrupt.
22 - clocks: Should contain the core clock and the AHB clock.
23 - clock-names: Should be "core" for the core clock and "iface" for the
27 - dmas: Should contain dma specifiers for transmit and receive channels
28 - dma-names: Should contain "tx" for transmit and "rx" for receive channels
29 - qcom,tx-crci: Identificator <u32> for Client Rate Control Interface to be
32 - qcom,rx-crci: Identificator <u32> for Client Rate Control Interface to be
37 The alias serialN will result in the UART being assigned port N.  If any
38 serialN alias exists, then an alias must exist for each enabled UART.  The
43 - A uartdm v1.4 device with dma capabilities.
46 		compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
50 		clock-names = "core", "iface";
52 		dma-names = "tx", "rx";
55 - A uartdm v1.3 device without dma capabilities and part of a GSBI complex.
58 		compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
63 		clock-names = "core", "iface";
66 - serialN alias.