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/linux/arch/arm/boot/dts/mediatek/
H A Dmt7623n.dtsi51 mmsys: syscon@14000000 { label
52 compatible = "mediatek,mt7623-mmsys",
53 "mediatek,mt2701-mmsys",
65 clocks = <&mmsys CLK_MM_SMI_LARB0>,
66 <&mmsys CLK_MM_SMI_LARB0>;
133 <&mmsys CLK_MM_SMI_COMMON>,
144 clocks = <&mmsys CLK_MM_DISP_OVL>;
153 clocks = <&mmsys CLK_MM_DISP_RDMA>;
162 clocks = <&mmsys CLK_MM_DISP_WDMA>;
171 clocks = <&mmsys CLK_MM_MDP_BLS_26M>,
[all …]
H A Dmt2701.dtsi193 <&mmsys CLK_MM_SMI_COMMON>,
514 mmsys: syscon@14000000 { label
515 compatible = "mediatek,mt2701-mmsys", "syscon";
524 clocks = <&mmsys CLK_MM_MDP_BLS_26M>, <&mmsys CLK_MM_DISP_BLS>;
534 clocks = <&mmsys CLK_MM_SMI_LARB0>,
535 <&mmsys CLK_MM_SMI_LARB0>;
/linux/Documentation/devicetree/bindings/display/mediatek/
H A Dmediatek,hdmi.yaml103 clocks = <&mmsys CLK_MM_HDMI_PIXEL>,
104 <&mmsys CLK_MM_HDMI_PLLCK>,
105 <&mmsys CLK_MM_HDMI_AUDIO>,
106 <&mmsys CLK_MM_HDMI_SPDIF>;
112 mediatek,syscon-hdmi = <&mmsys 0x900>;
H A Dmediatek,split.yaml18 Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
112 clocks = <&mmsys CLK_MM_DISP_SPLIT0>;
H A Dmediatek,color.yaml19 Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
119 clocks = <&mmsys CLK_MM_DISP_COLOR0>;
H A Dmediatek,merge.yaml18 Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
134 clocks = <&mmsys CLK_MM_DISP_MERGE>;
/linux/drivers/soc/mediatek/
H A Dmtk-mmsys.h106 * struct mtk_mmsys_driver_data - Settings of the mmsys
107 * @clk_driver: Clock driver name that the mmsys is using
109 * @routes: Routing table of the mmsys.
114 * @is_vppsys: Whether the mmsys is VPPSYS (Video Processing Pipe)
129 * Each MMSYS (multi-media system) may have different settings, they may use
H A Dmt8186-mmsys.h6 /* Values for DPI configuration in MMSYS address space */
/linux/arch/arm64/boot/dts/mediatek/
H A Dmt2712e.dtsi994 mmsys: syscon@14000000 { label
995 compatible = "mediatek,mt2712-mmsys", "syscon";
1006 clocks = <&mmsys CLK_MM_SMI_LARB0>,
1007 <&mmsys CLK_MM_SMI_LARB0>;
1015 clocks = <&mmsys CLK_MM_SMI_COMMON>,
1016 <&mmsys CLK_MM_SMI_COMMON>;
1026 clocks = <&mmsys CLK_MM_SMI_LARB4>,
1027 <&mmsys CLK_MM_SMI_LARB4>;
1037 clocks = <&mmsys CLK_MM_SMI_LARB5>,
1038 <&mmsys CLK_MM_SMI_LARB5>;
[all …]
/linux/Documentation/devicetree/bindings/media/
H A Dmediatek,mdp3-rdma.yaml18 Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
162 clocks = <&mmsys CLK_MM_MDP_RDMA0>,
163 <&mmsys CLK_MM_MDP_RSZ1>;
H A Dmediatek,mdp3-rsz.yaml72 clocks = <&mmsys CLK_MM_MDP_RSZ0>;
81 clocks = <&mmsys CLK_MM_MDP_RSZ1>;
H A Dmediatek,mdp3-wrot.yaml87 clocks = <&mmsys CLK_MM_MDP_WROT0>;
/linux/Documentation/devicetree/bindings/pwm/
H A Dmediatek,pwm-disp.yaml78 clocks = <&mmsys CLK_MM_DISP_PWM026M>,
79 <&mmsys CLK_MM_DISP_PWM0MM>;
/linux/include/dt-bindings/memory/
H A Dmt8186-memory-port.h32 /* LARB 0 -- MMSYS */
38 /* LARB 1 -- MMSYS */
45 /* LARB 2 -- MMSYS */
/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dmediatek,smi-common.yaml182 clocks = <&mmsys CLK_MM_SMI_COMMON>,
183 <&mmsys CLK_MM_SMI_COMMON>;
/linux/include/dt-bindings/reset/
H A Dmt8192-resets.h31 /* MMSYS resets */
H A Dmt8186-resets.h34 /* MMSYS resets */
H A Dmediatek,mt6795-resets.h17 /* MMSYS resets */
H A Dmt8173-resets.h30 /* MMSYS resets */
H A Dmt8183-resets.h83 /* MMSYS resets */
/linux/Documentation/devicetree/bindings/soc/mediatek/
H A Dmediatek,ccorr.yaml67 clocks = <&mmsys CLK_MM_MDP_CCORR>;
H A Dmediatek,wdma.yaml79 clocks = <&mmsys CLK_MM_MDP_WDMA0>;
/linux/drivers/clk/mediatek/
H A Dclk-mt6765-mm.c65 .compatible = "mediatek,mt6765-mmsys",
H A Dclk-mt6795-mm.c100 MODULE_DESCRIPTION("MediaTek MT6795 MMSYS clocks driver");
/linux/include/dt-bindings/clock/
H A Dmt8167-clk.h77 /* MMSYS */

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