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/linux/Documentation/devicetree/bindings/mmc/
H A Dsprd,sdhci-r11.yaml1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/mmc/sprd,sdhci-r11.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Orson Zhai <orsonzhai@gmail.com>
11 - Baolin Wang <baolin.wang7@gmail.com>
12 - Chunyan Zhang <zhang.lyra@gmail.com>
16 const: sprd,sdhci-r11
19 maxItems: 1
22 maxItems: 1
[all …]
H A Dbrcm,sdhci-brcmstb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mmc/brcm,sdhci-brcmstb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Al Cooper <alcooperx@gmail.com>
11 - Florian Fainelli <f.fainelli@gmail.com>
16 - items:
17 - enum:
18 - brcm,bcm7216-sdhci
19 - const: brcm,bcm7445-sdhci
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H A Dhisilicon,hi3798cv200-dw-mshc.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/mmc/hisilicon,hi3798cv200-dw-mshc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Yang Xiwen <forbidden405@outlook.com>
15 - hisilicon,hi3798cv200-dw-mshc
16 - hisilicon,hi3798mv200-dw-mshc
19 maxItems: 1
22 maxItems: 1
26 - description: bus interface unit clock
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H A Dsdhci-am654.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: http://devicetree.org/schemas/mmc/sdhci-am654.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: TI AM654 MMC Controller
11 - Ulf Hansson <ulf.hansson@linaro.org>
14 - $ref: sdhci-common.yaml#
19 - enum:
20 - ti,am62-sdhci
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/linux/arch/arm64/boot/dts/qcom/
H A Dipq9574-rdp418.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
5 * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
6 * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
9 /dts-v1/;
11 #include "ipq9574-rdp-common.dtsi"
14 model = "Qualcomm Technologies, Inc. IPQ9574/AP-AL02-C2";
15 compatible = "qcom,ipq9574-ap-al02-c2", "qcom,ipq9574";
20 pinctrl-0 = <&sdc_default_state>;
21 pinctrl-names = "default";
22 mmc-ddr-1_8v;
[all …]
H A Dipq5332-rdp441.dts1 // SPDX-License-Identifier: BSD-3-Clause
3 * IPQ5332 AP-MI01.2 board device tree source
5 * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
8 /dts-v1/;
10 #include "ipq5332-rdp-common.dtsi"
14 compatible = "qcom,ipq5332-ap-mi01.2", "qcom,ipq5332";
18 clock-frequency = <400000>;
19 pinctrl-0 = <&i2c_1_pins>;
20 pinctrl-names = "default";
25 bus-width = <4>;
[all …]
H A Dipq5332-rdp474.dts1 // SPDX-License-Identifier: BSD-3-Clause
5 * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
8 /dts-v1/;
10 #include "ipq5332-rdp-common.dtsi"
14 compatible = "qcom,ipq5332-ap-mi01.9", "qcom,ipq5332";
18 clock-frequency = <400000>;
19 pinctrl-0 = <&i2c_1_pins>;
20 pinctrl-names = "default";
25 bus-width = <4>;
26 max-frequency = <192000000>;
[all …]
H A Dipq5018-rdp432-c2.dts1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
3 * IPQ5018 MP03.1-C2 board device tree source
8 /dts-v1/;
13 model = "Qualcomm Technologies, Inc. IPQ5018/AP-RDP432.1-C2";
14 compatible = "qcom,ipq5018-rdp432-c2", "qcom,ipq5018";
21 stdout-path = "serial0:115200n8";
26 pinctrl-0 = <&uart1_pins>;
27 pinctrl-names = "default";
32 pinctrl-0 = <&sdc_default_state>;
33 pinctrl-names = "default";
[all …]
H A Dipq5332-rdp442.dts1 // SPDX-License-Identifier: BSD-3-Clause
8 /dts-v1/;
10 #include "ipq5332-rdp-common.dtsi"
14 compatible = "qcom,ipq5332-ap-mi01.3", "qcom,ipq5332";
18 clock-frequency = <400000>;
19 pinctrl-0 = <&i2c_1_pins>;
20 pinctrl-names = "default";
25 pinctrl-0 = <&spi_0_data_clk_pins &spi_0_cs_pins>;
26 pinctrl-names = "default";
30 compatible = "micron,n25q128a11", "jedec,spi-nor";
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H A Dipq5332-rdp468.dts1 // SPDX-License-Identifier: BSD-3-Clause
5 * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
8 /dts-v1/;
10 #include "ipq5332-rdp-common.dtsi"
14 compatible = "qcom,ipq5332-ap-mi01.6", "qcom,ipq5332";
16 regulator_fixed_5p0: regulator-s0500 {
17 compatible = "regulator-fixed";
18 regulator-min-microvolt = <500000>;
19 regulator-max-microvolt = <500000>;
20 regulator-boot-on;
[all …]
/linux/arch/arm64/boot/dts/mediatek/
H A Dmt7986a-bananapi-bpi-r3-emmc.dtso1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 /dts-v1/;
11 compatible = "bananapi,bpi-r3", "mediatek,mt7986a";
14 &{/soc/mmc@11230000} {
15 bus-width = <8>;
16 max-frequency = <200000000>;
17 cap-mmc-highspeed;
18 mmc-hs200-1_8v;
19 mmc-hs400-1_8v;
20 hs400-ds-delay = <0x14014>;
[all …]
/linux/arch/arm/boot/dts/rockchip/
H A Drk3288-tinker-s.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include "rk3288-tinker.dtsi"
12 compatible = "asus,rk3288-tinker-s", "rockchip,rk3288";
16 bus-width = <8>;
17 cap-mmc-highspeed;
18 non-removable;
19 pinctrl-names = "default";
20 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_pwr &emmc_bus8>;
21 max-frequency = <150000000>;
[all …]
/linux/arch/riscv/boot/dts/sophgo/
H A Dcv1812h-huashan-pi.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 /dts-v1/;
12 compatible = "sophgo,huashan-pi", "sophgo,cv1812h";
27 stdout-path = "serial0:115200n8";
30 reserved-memory {
31 #address-cells = <1>;
32 #size-cells = <1>;
37 no-map;
43 clock-frequency = <25000000>;
48 bus-width = <4>;
[all …]
/linux/arch/riscv/boot/dts/microchip/
H A Dmpfs-polarberry.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2020-2022 Microchip Technology Inc */
4 /dts-v1/;
7 #include "mpfs-polarberry-fabric.dtsi"
19 stdout-path = "serial0:115200n8";
38 phy-mode = "sgmii";
39 phy-handle = <&phy0>;
44 phy-mode = "sgmii";
45 phy-handle = <&phy1>;
48 phy1: ethernet-phy@5 {
[all …]
H A Dmpfs-sev-kit.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
4 /dts-v1/;
7 #include "mpfs-sev-kit-fabric.dtsi"
10 #address-cells = <2>;
11 #size-cells = <2>;
12 model = "Microchip PolarFire-SoC SEV Kit";
13 compatible = "microchip,mpfs-sev-kit", "microchip,mpfs";
25 stdout-path = "serial1:115200n8";
28 reserved-memory {
29 #address-cells = <2>;
[all …]
/linux/arch/arm64/boot/dts/sprd/
H A Dwhale2.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/clock/sprd,sc9860-clk.h>
11 interrupt-parent = <&gic>;
12 #address-cells = <2>;
13 #size-cells = <2>;
16 compatible = "simple-bus";
17 #address-cells = <2>;
18 #size-cells = <2>;
66 ap-apb@70000000 {
67 compatible = "simple-bus";
[all …]
/linux/arch/arm64/boot/dts/allwinner/
H A Dsun50i-h618-longan-module-3h.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include "sun50i-h616.dtsi"
7 #include "sun50i-h616-cpu-opp.dtsi"
10 cpu-supply = <&reg_dcdc2>;
14 pinctrl-names = "default";
15 pinctrl-0 = <&mmc2_pins>;
16 vmmc-supply = <&reg_dldo1>;
17 vqmmc-supply = <&reg_aldo1>;
18 bus-width = <8>;
19 non-removable;
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/linux/arch/arm64/boot/dts/freescale/
H A Dfsl-lx2162a-sr-som.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 // Device Tree file for LX2162A-SOM
5 // Copyright 2021 Rabeeh Khoury <rabeeh@solid-run.com>
6 // Copyright 2023 Josua Mayer <josua@solid-run.com>
13 phy-handle = <&ethernet_phy0>;
14 phy-connection-type = "rgmii-id";
20 ethernet_phy0: ethernet-phy@1 {
21 reg = <1>;
26 bus-width = <8>;
27 mmc-hs200-1_8v;
[all …]
/linux/arch/arm64/boot/dts/exynos/
H A Dexynos7885-jackpotlte.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung Galaxy A8 2018 (jackpotlte/SM-A530F) device tree source
9 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/input/input.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
18 chassis-type = "handset";
28 stdout-path = &serial_2;
38 gpio-keys {
39 compatible = "gpio-keys";
[all …]
/linux/arch/arm/boot/dts/samsung/
H A Dexynos5260-xyref5260.dts1 // SPDX-License-Identifier: GPL-2.0
9 /dts-v1/;
27 stdout-path = "serial2:115200n8";
31 compatible = "fixed-clock";
32 clock-frequency = <24000000>;
33 clock-output-names = "fin_pll";
34 #clock-cells = <0>;
37 ioclk_pcm: clock-pcm-ext {
38 compatible = "fixed-clock";
39 clock-frequency = <2048000>;
[all …]
/linux/arch/arm64/boot/dts/amlogic/
H A Dmeson-gxl-s905x-hwacom-amazetv.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 /dts-v1/;
10 #include "meson-gxl-s905x.dtsi"
13 compatible = "hwacom,amazetv", "amlogic,s905x", "amlogic,meson-gxl";
22 stdout-path = "serial0:115200n8";
30 vddio_card: gpio-regulator {
31 compatible = "regulator-gpio";
33 regulator-name = "VDDIO_CARD";
34 regulator-min-microvolt = <1800000>;
35 regulator-max-microvolt = <3300000>;
[all …]
H A Dmeson-gxl-s905x-nexbox-a95x.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 /dts-v1/;
10 #include "meson-gxl-s905x.dtsi"
13 compatible = "nexbox,a95x", "amlogic,s905x", "amlogic,meson-gxl";
22 stdout-path = "serial0:115200n8";
30 vddio_card: gpio-regulator {
31 compatible = "regulator-gpio";
33 regulator-name = "VDDIO_CARD";
34 regulator-min-microvolt = <1800000>;
35 regulator-max-microvolt = <3300000>;
[all …]
/linux/arch/arm64/boot/dts/rockchip/
H A Drk3328-nanopi-r2s-plus.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
9 /dts-v1/;
11 #include "rk3328-nanopi-r2s.dtsi"
14 compatible = "friendlyarm,nanopi-r2s-plus", "rockchip,rk3328";
23 bus-width = <8>;
24 cap-mmc-highspeed;
25 disable-wp;
26 mmc-hs200-1_8v;
27 non-removable;
28 pinctrl-names = "default";
[all …]
H A Drk3566-radxa-zero-3w.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 /dts-v1/;
5 #include "rk3566-radxa-zero-3.dtsi"
9 compatible = "radxa,zero-3w", "rockchip,rk3566";
17 sdio_pwrseq: sdio-pwrseq {
18 compatible = "mmc-pwrseq-simple";
19 clocks = <&rk817 1>;
20 clock-names = "ext_clock";
21 pinctrl-names = "default";
22 pinctrl-0 = <&wifi_reg_on_h>;
[all …]
/linux/arch/arm64/boot/dts/hisilicon/
H A Dhi3798cv200-poplar.dts1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
8 /dts-v1/;
10 #include <dt-bindings/gpio/gpio.h>
12 #include "poplar-pinctrl.dtsi"
16 compatible = "hisilicon,hi3798cv200-poplar", "hisilicon,hi3798cv200";
24 stdout-path = "serial0:115200n8";
33 compatible = "gpio-leds";
35 user-led0 {
38 linux,default-trigger = "heartbeat";
[all …]

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