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/freebsd/sys/contrib/device-tree/Bindings/memory-controllers/fsl/
H A Dfsl,ddr.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/fsl/fsl,ddr.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale DDR memory controller
10 - Borislav Petkov <bp@alien8.de>
11 - York Sun <york.sun@nxp.com>
15 pattern: "^memory-controller@[0-9a-f]+$"
19 - items:
20 - enum:
[all …]
H A Dddr.txt1 Freescale DDR memory controller
5 - compatible : Should include "fsl,chip-memory-controller" where
7 "fsl,qoriq-memory-controller".
8 - reg : Address and size of DDR controller registers
9 - interrupts : Error interrupt of DDR controller
10 - little-endian : Specifies little-endian access to registers
11 If omitted, big-endian will be used.
15 memory-controller@2000 {
16 compatible = "fsl,bsc9132-memory-controller";
24 ddr1: memory-controller@8000 {
[all …]
/freebsd/stand/efi/include/
H A Defipciio.h2 EFI PCI I/O Protocol provides the basic Memory, I/O, PCI configuration,
3 and DMA interfaces that a driver uses to access its PCI controller.
5 Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
9 http://opensource.org/licenses/bsd-license.php
54 #define EFI_PCI_IO_PASS_THROUGH_BAR 0xff ///< Special BAR that passes a memory or …
55 #define EFI_PCI_IO_ATTRIBUTE_MASK 0x077f ///< All the following I/O and Memory cyc…
56 #define EFI_PCI_IO_ATTRIBUTE_ISA_MOTHERBOARD_IO 0x0001 ///< I/O cycles 0x0000-0x00FF (10 bit dec…
57 #define EFI_PCI_IO_ATTRIBUTE_ISA_IO 0x0002 ///< I/O cycles 0x0100-0x03FF or greater …
59 #define EFI_PCI_IO_ATTRIBUTE_VGA_MEMORY 0x0008 ///< MEM cycles 0xA0000-0xBFFFF (24 bit d…
60 #define EFI_PCI_IO_ATTRIBUTE_VGA_IO 0x0010 ///< I/O cycles 0x3B0-0x3BB and 0x3C0-0x3…
[all …]
/freebsd/sys/dev/isci/
H A Disci.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
6 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
56 MALLOC_DEFINE(M_ISCI, "isci", "isci driver memory allocations");
92 { 0x1d608086, "Intel(R) C600 Series Chipset SAS Controller" },
93 { 0x1d618086, "Intel(R) C600 Series Chipset SAS Controller (SATA mode)" },
94 { 0x1d628086, "Intel(R) C600 Series Chipset SAS Controller" },
189 struct ISCI_CONTROLLER *controller = &isci->controllers[i]; isci_detach() local
348 struct ISCI_CONTROLLER *controller = &isci->controllers[index]; isci_initialize() local
395 struct ISCI_MEMORY *memory = (struct ISCI_MEMORY *)arg; isci_allocate_dma_buffer_callback() local
407 isci_allocate_dma_buffer(device_t device,struct ISCI_CONTROLLER * controller,struct ISCI_MEMORY * memory) isci_allocate_dma_buffer() argument
408 isci_allocate_dma_buffer(device_t device,struct ISCI_CONTROLLER * controller,struct ISCI_MEMORY * memory) isci_allocate_dma_buffer() argument
462 scif_cb_lock_associate(SCI_CONTROLLER_HANDLE_T controller,SCI_LOCK_HANDLE_T lock) scif_cb_lock_associate() argument
483 scif_cb_lock_disassociate(SCI_CONTROLLER_HANDLE_T controller,SCI_LOCK_HANDLE_T lock) scif_cb_lock_disassociate() argument
501 scif_cb_lock_acquire(SCI_CONTROLLER_HANDLE_T controller,SCI_LOCK_HANDLE_T lock) scif_cb_lock_acquire() argument
517 scif_cb_lock_release(SCI_CONTROLLER_HANDLE_T controller,SCI_LOCK_HANDLE_T lock) scif_cb_lock_release() argument
533 scif_cb_start_internal_io_task_create(SCI_CONTROLLER_HANDLE_T controller) scif_cb_start_internal_io_task_create() argument
649 scic_cb_pci_get_bar(SCI_CONTROLLER_HANDLE_T controller,uint16_t bar_number) scic_cb_pci_get_bar() argument
673 scic_cb_port_invalid_link_up(SCI_CONTROLLER_HANDLE_T controller,SCI_PORT_HANDLE_T port,SCI_PHY_HANDLE_T phy) scic_cb_port_invalid_link_up() argument
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/freebsd/share/man/man4/
H A Dbce.41 .\" Copyright (c) 2006-2014 QLogic Corporation
35 .Bd -ragged -offset indent
43 .Bd -literal -offset indent
55 same controller.
62 .Bl -item -offset indent -compact
72 10/100/1000Mbps operation in full-duplex mode
74 10/100Mbps operation in half-duplex mode
80 .Bl -tag -width ".Cm 10baseT/UTP"
92 .Cm full-duplex
94 .Cm half-duplex
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/freebsd/sys/contrib/device-tree/Bindings/memory-controllers/
H A Dnuvoton,npcm-memory-controller.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nuvoton,npcm-memory-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Nuvoton NPCM Memory Controller
10 - Marvin Lin <kflin@nuvoton.com>
11 - Stanley Chu <yschu@nuvoton.com>
14 The Nuvoton BMC SoC supports DDR4 memory with or without ECC (error correction
17 The memory controller supports single bit error correction, double bit error
18 detection (in-line ECC in which a section (1/8th) of the memory device used to
[all …]
H A Dnvidia,tegra210-emc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra210-emc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra210 SoC External Memory Controller
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
14 The EMC interfaces with the off-chip SDRAM to service the request stream
15 sent from the memory controller.
19 const: nvidia,tegra210-emc
[all …]
H A Dnvidia,tegra186-mc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra186-mc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra186 (and later) SoC Memory Controller
10 - Jon Hunter <jonathanh@nvidia.com>
11 - Thierry Reding <thierry.reding@gmail.com>
14 The NVIDIA Tegra186 SoC features a 128 bit memory controller that is split
16 handles memory requests for 40-bit virtual addresses from internal clients
17 and arbitrates among them to allocate memory bandwidth.
[all …]
H A Darm,pl353-smc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/arm,pl353-smc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM PL353 Static Memory Controller (SMC) device-tree bindings
10 - Miquel Raynal <miquel.raynal@bootlin.com>
11 - Naga Sureshkumar Relli <naga.sureshkumar.relli@xilinx.com>
14 The PL353 Static Memory Controller is a bus where you can connect two kinds
15 of memory interfaces, which are NAND and memory mapped interfaces (such as
23 const: arm,pl353-smc-r2p1
[all …]
H A Darm,pl35x-smc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/arm,pl35x-smc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Arm PL35x Series Static Memory Controller (SMC)
10 - Miquel Raynal <miquel.raynal@bootlin.com>
13 The PL35x Static Memory Controller is a bus where you can connect two kinds
14 of memory interfaces, which are NAND and memory mapped interfaces (such as
18 https://documentation-service.arm.com/static/5e8e2524fd977155116a58aa
26 - arm,pl353-smc-r2p1
[all …]
H A Dnvidia,tegra20-mc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra20-mc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra20 SoC Memory Controller
10 - Dmitry Osipenko <digetx@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Thierry Reding <thierry.reding@gmail.com>
15 The Tegra20 Memory Controller merges request streams from various client
16 interfaces into request stream(s) for the various memory target devices,
[all …]
H A Dsnps,dw-umctl2-ddrc.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/snps,dw-umctl2-ddrc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DesignWare Universal Multi-Protocol Memory Controller
10 - Krzysztof Kozlowski <krzk@kernel.org>
11 - Michal Simek <michal.simek@amd.com>
14 Synopsys DesignWare Enhanced uMCTL2 DDR Memory Controller is capable of
15 working with the memory devices supporting up to (LP)DDR4 protocol. It can
17 16-bits or 32-bits or 64-bits wide.
[all …]
H A Dexynos5422-dmc.txt1 * Exynos5422 frequency and voltage scaling for Dynamic Memory Controller device
3 The Samsung Exynos5422 SoC has DMC (Dynamic Memory Controller) to which the DRAM
4 memory chips are connected. The driver is to monitor the controller in runtime
5 and switch frequency and voltage. To monitor the usage of the controller in
7 is able to measure the current load of the memory.
9 switch the DMC and memory frequency.
12 - compatible: Should be "samsung,exynos5422-dmc".
13 - clocks : list of clock specifiers, must contain an entry for each
14 required entry in clock-names for CLK_FOUT_SPLL, CLK_MOUT_SCLK_SPLL,
17 - clock-names : should include "fout_spll", "mout_sclk_spll", "ff_dout_spll2",
[all …]
/freebsd/sys/dev/isci/scil/
H A Dscic_sds_pci.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause OR GPL-2.0
9 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
22 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
28 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
70 * determine the virtual memory space for the controller registers
72 * @param[in] this_controller The controller for which to read the base
86 this_controller->lex_registers = in scic_sds_pci_bar_initialization()
89 this_controller->smu_registers = in scic_sds_pci_bar_initialization()
91 this_controller->scu_registers = in scic_sds_pci_bar_initialization()
[all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/tremontx/
H A Duncore-memory.json3 "BriefDescription": "read requests to memory controller. Derived from unc_m_cas_count.rd",
14 "BriefDescription": "read requests to memory controller",
25 "BriefDescription": "write requests to memory controller. Derived from unc_m_cas_count.wr",
36 "BriefDescription": "write requests to memory controller",
47 "BriefDescription": "Memory controller clock ticks",
55 "BriefDescription": "Pre-charge for reads",
65 "BriefDescription": "Pre-charge for writes",
168 …memory controller and to track the requests. Requests allocate into the RPQ soon after they enter…
179 …memory controller and to track the requests. Requests allocate into the RPQ soon after they enter…
190 …memory controller and to track the requests. Requests allocate into the RPQ soon after they enter…
[all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/skylakex/
H A Duncore-memory.json3 "BriefDescription": "read requests to memory controller. Derived from unc_m_cas_count.rd",
13 "BriefDescription": "read requests to memory controller",
23 "BriefDescription": "write requests to memory controller. Derived from unc_m_cas_count.wr",
33 "BriefDescription": "write requests to memory controller",
43 "BriefDescription": "Memory controller clock ticks",
60 "BriefDescription": "Cycles Memory is in self refresh power mode",
70 "BriefDescription": "Pre-charges due to page misses",
79 "BriefDescription": "Pre-charge for reads",
93 …te commands sent on this channel due to a write request to the iMC (Memory Controller). Activate …
103 …on": "Counts all CAS (Column Address Select) commands issued to DRAM per memory channel. CAS comm…
[all …]
/freebsd/sys/contrib/device-tree/Bindings/display/tegra/
H A Dnvidia,tegra20-host1x.txt4 - compatible: "nvidia,tegra<chip>-host1x"
5 - reg: Physical base address and length of the controller's registers.
6 For pre-Tegra186, one entry describing the whole register area.
7 For Tegra186, one entry for each entry in reg-names:
8 "vm" - VM region assigned to Linux
9 "hypervisor" - Hypervisor region (only if Linux acts as hypervisor)
10 - interrupts: The interrupt outputs from the controller.
11 - #address-cells: The number of cells used to represent physical base addresses
13 - #size-cells: The number of cells used to represent the size of an address
15 - ranges: The mapping of the host1x address space to the CPU address space.
[all …]
H A Dnvidia,tegra20-dc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-dc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra Display Controller
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 pattern: "^dc@[0-9a-f]+$"
19 - enum:
20 - nvidia,tegra20-dc
[all …]
/freebsd/sys/contrib/device-tree/Bindings/ata/
H A Dapm-xgene.txt1 * APM X-Gene 6.0 Gb/s SATA host controller nodes
3 SATA host controller nodes are defined to describe on-chip Serial ATA
4 controllers. Each SATA controller (pair of ports) have its own node.
7 - compatible : Shall contain:
8 * "apm,xgene-ahci"
9 - reg : First memory resource shall be the AHCI memory
11 Second memory resource shall be the host controller
12 core memory resource.
13 Third memory resource shall be the host controller
14 diagnostic memory resource.
[all …]
/freebsd/sys/contrib/device-tree/Bindings/edac/
H A Dapm-xgene-edac.txt1 * APM X-Gene SoC EDAC node
3 EDAC node is defined to describe on-chip error detection and correction.
6 memory controller - Memory controller
7 PMD (L1/L2) - Processor module unit (PMD) L1/L2 cache
8 L3 - L3 cache controller
9 SoC - SoC IP's such as Ethernet, SATA, and etc
14 - compatible : Shall be "apm,xgene-edac".
15 - regmap-csw : Regmap of the CPU switch fabric (CSW) resource.
16 - regmap-mcba : Regmap of the MCB-A (memory bridge) resource.
17 - regmap-mcbb : Regmap of the MCB-B (memory bridge) resource.
[all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/cascadelakex/
H A Duncore-memory.json3 "BriefDescription": "read requests to memory controller. Derived from unc_m_cas_count.rd",
13 "BriefDescription": "read requests to memory controller",
23 "BriefDescription": "write requests to memory controller. Derived from unc_m_cas_count.wr",
33 "BriefDescription": "write requests to memory controller",
43 "BriefDescription": "Memory controller clock ticks",
60 "BriefDescription": "Cycles Memory is in self refresh power mode",
70 "BriefDescription": "Pre-charges due to page misses",
79 "BriefDescription": "Pre-charge for reads",
88 …": "Write requests allocated in the PMM Write Pending Queue for Intel Optane DC persistent memory",
96 …": "Write requests allocated in the PMM Write Pending Queue for Intel Optane DC persistent memory",
[all …]
/freebsd/sys/contrib/device-tree/Bindings/mips/brcm/
H A Dsoc.txt5 - compatible: "brcm,bcm3368", "brcm,bcm3384", "brcm,bcm33843"
6 "brcm,bcm3384-viper", "brcm,bcm33843-viper"
12 The experimental -viper variants are for running Linux on the 3384's
16 ----------------
21 = Always-On control block (AON CTRL)
23 This hardware provides control registers for the "always-on" (even in low-power
27 - compatible : should be one of
28 "brcm,bcm7425-aon-ctrl"
29 "brcm,bcm7429-aon-ctrl"
30 "brcm,bcm7435-aon-ctrl" and
[all …]
/freebsd/sys/contrib/device-tree/Bindings/mfd/
H A Daspeed-lpc.txt2 Device tree bindings for the Aspeed Low Pin Count (LPC) Bus Controller
5 The LPC bus is a means to bridge a host CPU to a number of low-bandwidth
7 primary use case of the Aspeed LPC controller is as a slave on the bus
8 (typically in a Baseboard Management Controller SoC), but under certain
11 The LPC controller is represented as a multi-function device to account for the
14 * An IPMI Block Transfer[2] Controller
16 * An LPC Host Controller: Manages LPC functions such as host vs slave mode, the
18 APB-to-LPC bridging amonst other functions.
20 * An LPC Host Interface Controller: Manages functions exposed to the host such
21 as LPC firmware hub cycles, configuration of the LPC-to-AHB mapping, UART
[all …]
/freebsd/sys/contrib/device-tree/Bindings/mtd/
H A Daspeed-smc.txt1 * Aspeed Firmware Memory controller
2 * Aspeed SPI Flash Memory Controller
4 The Firmware Memory Controller in the Aspeed AST2500 SoC supports
8 The two SPI flash memory controllers in the AST2500 each support two
12 - compatible : Should be one of
13 "aspeed,ast2400-fmc" for the AST2400 Firmware Memory Controller
14 "aspeed,ast2400-spi" for the AST2400 SPI Flash memory Controller
15 "aspeed,ast2500-fmc" for the AST2500 Firmware Memory Controller
16 "aspeed,ast2500-spi" for the AST2500 SPI flash memory controllers
18 - reg : the first contains the control register location and length,
[all …]
/freebsd/sys/contrib/device-tree/Bindings/dma/
H A Dstericsson,dma40.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ST-Ericsso
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