Lines Matching +full:memory +full:- +full:controller
4 - compatible: "nvidia,tegra<chip>-host1x"
5 - reg: Physical base address and length of the controller's registers.
6 For pre-Tegra186, one entry describing the whole register area.
7 For Tegra186, one entry for each entry in reg-names:
8 "vm" - VM region assigned to Linux
9 "hypervisor" - Hypervisor region (only if Linux acts as hypervisor)
10 - interrupts: The interrupt outputs from the controller.
11 - #address-cells: The number of cells used to represent physical base addresses
13 - #size-cells: The number of cells used to represent the size of an address
15 - ranges: The mapping of the host1x address space to the CPU address space.
16 - clocks: Must contain one entry, for the module clock.
17 See ../clocks/clock-bindings.txt for details.
18 - resets: Must contain an entry for each entry in reset-names.
20 - reset-names: Must include the following entries:
21 - host1x
22 - mc
25 - operating-points-v2: See ../bindings/opp/opp.txt for details.
26 - power-domains: Phandle to HEG or core power domain.
28 For each opp entry in 'operating-points-v2' table of host1x and its modules:
29 - opp-supported-hw: One bitfield indicating:
36 Each host1x client module having to perform DMA through the Memory Controller
37 should have the interconnect endpoints set to the Memory Client and External
38 Memory respectively.
40 The host1x top-level node defines a number of children, each representing one
43 - mpe: video encoder
46 - compatible: "nvidia,tegra<chip>-mpe"
47 - reg: Physical base address and length of the controller's registers.
48 - interrupts: The interrupt outputs from the controller.
49 - clocks: Must contain one entry, for the module clock.
50 See ../clocks/clock-bindings.txt for details.
51 - resets: Must contain an entry for each entry in reset-names.
53 - reset-names: Must include the following entries:
54 - mpe
57 - interconnects: Must contain entry for the MPE memory clients.
58 - interconnect-names: Must include name of the interconnect path for each
60 available memory clients, see MEMORY CONTROLLER section.
61 - operating-points-v2: See ../bindings/opp/opp.txt for details.
62 - power-domains: Phandle to MPE power domain.
64 - vi: video input
67 - compatible: "nvidia,tegra<chip>-vi"
68 - reg: Physical base address and length of the controller registers.
69 - interrupts: The interrupt outputs from the controller.
70 - clocks: clocks: Must contain one entry, for the module clock.
71 See ../clocks/clock-bindings.txt for details.
72 - Tegra20/Tegra30/Tegra114/Tegra124:
73 - resets: Must contain an entry for each entry in reset-names.
75 - reset-names: Must include the following entries:
76 - vi
77 - Tegra210:
78 - power-domains: Must include venc powergate node as vi is in VE partition.
84 Documentation/devicetree/bindings/media/video-interfaces.txt
90 - csi: mipi csi interface to vi
93 - compatible: "nvidia,tegra210-csi"
94 - reg: Physical base address offset to parent and length of the controller
96 - clocks: Must contain entries csi, cilab, cilcd, cile, csi_tpg clocks.
97 See ../clocks/clock-bindings.txt for details.
98 - power-domains: Must include sor powergate node as csicil is in
106 - reg: csi port number. Valid port numbers are 0 through 5.
107 - nvidia,mipi-calibrate: Should contain a phandle and a specifier
109 calibrated. See also ../display/tegra/nvidia,tegra114-mipi.txt.
117 Documentation/devicetree/bindings/media/video-interfaces.txt
125 - reg: 0
129 - data-lanes: an array of data lane from 1 to 8. Valid array
131 - remote-endpoint: phandle to sensor 'endpoint' node.
135 - reg: 1
139 - remote-endpoint: phandle to vi port 'endpoint' node.
142 - interconnects: Must contain entry for the VI memory clients.
143 - interconnect-names: Must include name of the interconnect path for each
145 available memory clients, see MEMORY CONTROLLER section.
146 - operating-points-v2: See ../bindings/opp/opp.txt for details.
147 - power-domains: Phandle to VENC power domain.
149 - epp: encoder pre-processor
152 - compatible: "nvidia,tegra<chip>-epp"
153 - reg: Physical base address and length of the controller's registers.
154 - interrupts: The interrupt outputs from the controller.
155 - clocks: Must contain one entry, for the module clock.
156 See ../clocks/clock-bindings.txt for details.
157 - resets: Must contain an entry for each entry in reset-names.
159 - reset-names: Must include the following entries:
160 - epp
163 - interconnects: Must contain entry for the EPP memory clients.
164 - interconnect-names: Must include name of the interconnect path for each
166 available memory clients, see MEMORY CONTROLLER section.
167 - operating-points-v2: See ../bindings/opp/opp.txt for details.
168 - power-domains: Phandle to HEG or core power domain.
170 - isp: image signal processor
173 - compatible: "nvidia,tegra<chip>-isp"
174 - reg: Physical base address and length of the controller's registers.
175 - interrupts: The interrupt outputs from the controller.
176 - clocks: Must contain one entry, for the module clock.
177 See ../clocks/clock-bindings.txt for details.
178 - resets: Must contain an entry for each entry in reset-names.
180 - reset-names: Must include the following entries:
181 - isp
184 - interconnects: Must contain entry for the ISP memory clients.
185 - interconnect-names: Must include name of the interconnect path for each
187 available memory clients, see MEMORY CONTROLLER section.
188 - power-domains: Phandle to VENC or core power domain.
190 - gr2d: 2D graphics engine
193 - compatible: "nvidia,tegra<chip>-gr2d"
194 - reg: Physical base address and length of the controller's registers.
195 - interrupts: The interrupt outputs from the controller.
196 - clocks: Must contain one entry, for the module clock.
197 See ../clocks/clock-bindings.txt for details.
198 - resets: Must contain an entry for each entry in reset-names.
200 - reset-names: Must include the following entries:
201 - 2d
202 - mc
205 - interconnects: Must contain entry for the GR2D memory clients.
206 - interconnect-names: Must include name of the interconnect path for each
208 available memory clients, see MEMORY CONTROLLER section.
209 - operating-points-v2: See ../bindings/opp/opp.txt for details.
210 - power-domains: Phandle to HEG or core power domain.
212 - gr3d: 3D graphics engine
215 - compatible: "nvidia,tegra<chip>-gr3d"
216 - reg: Physical base address and length of the controller's registers.
217 - clocks: Must contain an entry for each entry in clock-names.
218 See ../clocks/clock-bindings.txt for details.
219 - clock-names: Must include the following entries:
221 - 3d
223 - 3d2 (Only required on SoCs with two 3D clocks)
224 - resets: Must contain an entry for each entry in reset-names.
226 - reset-names: Must include the following entries:
227 - 3d
228 - 3d2 (Only required on SoCs with two 3D clocks)
229 - mc
230 - mc2 (Only required on SoCs with two 3D clocks)
233 - interconnects: Must contain entry for the GR3D memory clients.
234 - interconnect-names: Must include name of the interconnect path for each
236 available memory clients, see MEMORY CONTROLLER section.
237 - operating-points-v2: See ../bindings/opp/opp.txt for details.
238 - power-domains: Phandles to 3D or core power domain.
240 - dc: display controller
243 - compatible: "nvidia,tegra<chip>-dc"
244 - reg: Physical base address and length of the controller's registers.
245 - interrupts: The interrupt outputs from the controller.
246 - clocks: Must contain an entry for each entry in clock-names.
247 See ../clocks/clock-bindings.txt for details.
248 - clock-names: Must include the following entries:
249 - dc
251 - parent
252 - resets: Must contain an entry for each entry in reset-names.
254 - reset-names: Must include the following entries:
255 - dc
256 - nvidia,head: The number of the display controller head. This is used to
260 Each display controller node has a child node, named "rgb", that represents
261 the RGB output associated with the controller. It can take the following
263 - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
264 - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection
265 - nvidia,edid: supplies a binary EDID blob
266 - nvidia,panel: phandle of a display panel
267 - interconnects: Must contain entry for the DC memory clients.
268 - interconnect-names: Must include name of the interconnect path for each
270 available memory clients, see MEMORY CONTROLLER section.
271 - operating-points-v2: See ../bindings/opp/opp.txt for details.
272 - power-domains: Phandle to core power domain.
274 - hdmi: High Definition Multimedia Interface
277 - compatible: "nvidia,tegra<chip>-hdmi"
278 - reg: Physical base address and length of the controller's registers.
279 - interrupts: The interrupt outputs from the controller.
280 - hdmi-supply: supply for the +5V HDMI connector pin
281 - vdd-supply: regulator for supply voltage
282 - pll-supply: regulator for PLL
283 - clocks: Must contain an entry for each entry in clock-names.
284 See ../clocks/clock-bindings.txt for details.
285 - clock-names: Must include the following entries:
286 - hdmi
288 - parent
289 - resets: Must contain an entry for each entry in reset-names.
291 - reset-names: Must include the following entries:
292 - hdmi
295 - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
296 - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection
297 - nvidia,edid: supplies a binary EDID blob
298 - nvidia,panel: phandle of a display panel
299 - operating-points-v2: See ../bindings/opp/opp.txt for details.
301 - tvo: TV encoder output
304 - compatible: "nvidia,tegra<chip>-tvo"
305 - reg: Physical base address and length of the controller's registers.
306 - interrupts: The interrupt outputs from the controller.
307 - clocks: Must contain one entry, for the module clock.
308 See ../clocks/clock-bindings.txt for details.
311 - operating-points-v2: See ../bindings/opp/opp.txt for details.
312 - power-domains: Phandle to core power domain.
314 - dsi: display serial interface
317 - compatible: "nvidia,tegra<chip>-dsi"
318 - reg: Physical base address and length of the controller's registers.
319 - clocks: Must contain an entry for each entry in clock-names.
320 See ../clocks/clock-bindings.txt for details.
321 - clock-names: Must include the following entries:
322 - dsi
324 - lp
325 - parent
326 - resets: Must contain an entry for each entry in reset-names.
328 - reset-names: Must include the following entries:
329 - dsi
330 - avdd-dsi-supply: phandle of a supply that powers the DSI controller
331 - nvidia,mipi-calibrate: Should contain a phandle and a specifier specifying
333 ../display/tegra/nvidia,tegra114-mipi.txt.
336 - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
337 - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection
338 - nvidia,edid: supplies a binary EDID blob
339 - nvidia,panel: phandle of a display panel
340 - nvidia,ganged-mode: contains a phandle to a second DSI controller to gang
342 - operating-points-v2: See ../bindings/opp/opp.txt for details.
344 - sor: serial output resource
347 - compatible: Should be:
348 - "nvidia,tegra124-sor": for Tegra124 and Tegra132
349 - "nvidia,tegra132-sor": for Tegra132
350 - "nvidia,tegra210-sor": for Tegra210
351 - "nvidia,tegra210-sor1": for Tegra210
352 - "nvidia,tegra186-sor": for Tegra186
353 - "nvidia,tegra186-sor1": for Tegra186
354 - reg: Physical base address and length of the controller's registers.
355 - interrupts: The interrupt outputs from the controller.
356 - clocks: Must contain an entry for each entry in clock-names.
357 See ../clocks/clock-bindings.txt for details.
358 - clock-names: Must include the following entries:
359 - sor: clock input for the SOR hardware
360 - out: SOR output clock
361 - parent: input for the pixel clock
362 - dp: reference clock for the SOR clock
363 - safe: safe reference for the SOR clock during power up
366 - pad: SOR pad output clock (on Tegra186 and later)
369 - source: source clock for the SOR clock (obsolete, use "out" instead)
371 - resets: Must contain an entry for each entry in reset-names.
373 - reset-names: Must include the following entries:
374 - sor
377 - nvidia,interface: index of the SOR interface
380 - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
381 - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection
382 - nvidia,edid: supplies a binary EDID blob
383 - nvidia,panel: phandle of a display panel
384 - nvidia,xbar-cfg: 5 cells containing the crossbar configuration. Each lane
389 - nvidia,dpaux: phandle to a DispayPort AUX interface
391 - dpaux: DisplayPort AUX interface
392 - compatible : Should contain one of the following:
393 - "nvidia,tegra124-dpaux": for Tegra124 and Tegra132
394 - "nvidia,tegra210-dpaux": for Tegra210
395 - reg: Physical base address and length of the controller's registers.
396 - interrupts: The interrupt outputs from the controller.
397 - clocks: Must contain an entry for each entry in clock-names.
398 See ../clocks/clock-bindings.txt for details.
399 - clock-names: Must include the following entries:
400 - dpaux: clock input for the DPAUX hardware
401 - parent: reference clock
402 - resets: Must contain an entry for each entry in reset-names.
404 - reset-names: Must include the following entries:
405 - dpaux
406 - vdd-supply: phandle of a supply that powers the DisplayPort link
407 - i2c-bus: Subnode where I2C slave devices are listed. This subnode
411 See ../pinctrl/nvidia,tegra124-dpaux-padctl.txt for information
412 regarding the DPAUX pad controller bindings.
414 - vic: Video Image Compositor
415 - compatible : "nvidia,tegra<chip>-vic"
416 - reg: Physical base address and length of the controller's registers.
417 - interrupts: The interrupt outputs from the controller.
418 - clocks: Must contain an entry for each entry in clock-names.
419 See ../clocks/clock-bindings.txt for details.
420 - clock-names: Must include the following entries:
421 - vic: clock input for the VIC hardware
422 - resets: Must contain an entry for each entry in reset-names.
424 - reset-names: Must include the following entries:
425 - vic
428 - interconnects: Must contain entry for the VIC memory clients.
429 - interconnect-names: Must include name of the interconnect path for each
431 available memory clients, see MEMORY CONTROLLER section.
439 compatible = "nvidia,tegra20-host1x", "simple-bus";
445 reset-names = "host1x";
446 operating-points-v2 = <&dvfs_opp_table>;
447 power-domains = <&domain>;
449 #address-cells = <1>;
450 #size-cells = <1>;
455 compatible = "nvidia,tegra20-mpe";
460 reset-names = "mpe";
461 operating-points-v2 = <&dvfs_opp_table>;
462 power-domains = <&domain>;
466 compatible = "nvidia,tegra210-vi";
469 assigned-clocks = <&tegra_car TEGRA210_CLK_VI>;
470 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
471 operating-points-v2 = <&dvfs_opp_table>;
474 power-domains = <&pd_venc>;
476 #address-cells = <1>;
477 #size-cells = <1>;
482 #address-cells = <1>;
483 #size-cells = <0>;
488 remote-endpoint = <&imx219_csi_out0>;
494 compatible = "nvidia,tegra210-csi";
496 assigned-clocks = <&tegra_car TEGRA210_CLK_CILAB>,
500 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>,
503 assigned-clock-rates = <102000000>,
513 clock-names = "csi", "cilab", "cilcd", "cile", "csi_tpg";
514 power-domains = <&pd_sor>;
516 #address-cells = <1>;
517 #size-cells = <0>;
521 nvidia,mipi-calibrate = <&mipi 0x001>;
524 #address-cells = <1>;
525 #size-cells = <0>;
530 data-lanes = <1 2>;
531 remote-endpoint = <&imx219_out0>;
538 remote-endpoint = <&imx219_vi_in0>;
547 compatible = "nvidia,tegra20-epp";
552 reset-names = "epp";
553 operating-points-v2 = <&dvfs_opp_table>;
554 power-domains = <&domain>;
558 compatible = "nvidia,tegra20-isp";
563 reset-names = "isp";
567 compatible = "nvidia,tegra20-gr2d";
572 reset-names = "2d";
573 operating-points-v2 = <&dvfs_opp_table>;
574 power-domains = <&domain>;
578 compatible = "nvidia,tegra20-gr3d";
582 reset-names = "3d";
583 operating-points-v2 = <&dvfs_opp_table>;
584 power-domains = <&domain>;
588 compatible = "nvidia,tegra20-dc";
593 clock-names = "dc", "parent";
595 reset-names = "dc";
596 operating-points-v2 = <&dvfs_opp_table>;
597 power-domains = <&domain>;
603 interconnect-names = "wina",
614 compatible = "nvidia,tegra20-dc";
619 clock-names = "dc", "parent";
621 reset-names = "dc";
622 operating-points-v2 = <&dvfs_opp_table>;
623 power-domains = <&domain>;
629 interconnect-names = "wina",
640 compatible = "nvidia,tegra20-hdmi";
645 clock-names = "hdmi", "parent";
647 reset-names = "hdmi";
649 operating-points-v2 = <&dvfs_opp_table>;
653 compatible = "nvidia,tegra20-tvo";
658 operating-points-v2 = <&dvfs_opp_table>;
662 compatible = "nvidia,tegra20-dsi";
666 clock-names = "dsi", "parent";
668 reset-names = "dsi";
670 operating-points-v2 = <&dvfs_opp_table>;