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Searched full:membase (Results 1 – 25 of 164) sorted by relevance

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/linux/drivers/tty/serial/
H A Dmilbeaut_usio.c67 writew(readw(port->membase + MLB_USIO_REG_FCR) & ~MLB_USIO_FCR_FTIE, in mlb_usio_stop_tx()
68 port->membase + MLB_USIO_REG_FCR); in mlb_usio_stop_tx()
69 writeb(readb(port->membase + MLB_USIO_REG_SCR) & ~MLB_USIO_SCR_TBIE, in mlb_usio_stop_tx()
70 port->membase + MLB_USIO_REG_SCR); in mlb_usio_stop_tx()
78 writew(readw(port->membase + MLB_USIO_REG_FCR) & ~MLB_USIO_FCR_FTIE, in mlb_usio_tx_chars()
79 port->membase + MLB_USIO_REG_FCR); in mlb_usio_tx_chars()
80 writeb(readb(port->membase + MLB_USIO_REG_SCR) & in mlb_usio_tx_chars()
82 port->membase + MLB_USIO_REG_SCR); in mlb_usio_tx_chars()
85 writew(port->x_char, port->membase + MLB_USIO_REG_DR); in mlb_usio_tx_chars()
96 (readw(port->membase + MLB_USIO_REG_FBYTE) & 0xff); in mlb_usio_tx_chars()
[all …]
H A Dqcom_geni_serial.c194 writel(rfr, uport->membase + SE_UART_MANUAL_RFR); in qcom_geni_set_rs485_mode()
202 uport->membase = devm_platform_ioremap_resource(pdev, 0); in qcom_geni_serial_request_port()
203 if (IS_ERR(uport->membase)) in qcom_geni_serial_request_port()
204 return PTR_ERR(uport->membase); in qcom_geni_serial_request_port()
205 port->se.base = uport->membase; in qcom_geni_serial_request_port()
225 geni_ios = readl(uport->membase + SE_GENI_IOS); in qcom_geni_serial_get_mctrl()
247 writel(uart_manual_rfr, uport->membase + SE_UART_MANUAL_RFR); in qcom_geni_serial_set_mctrl()
292 return readl(uport->membase + SE_GENI_STATUS) & M_GENI_CMD_ACTIVE; in qcom_geni_serial_main_active()
297 return readl(uport->membase + SE_GENI_STATUS) & S_GENI_CMD_ACTIVE; in qcom_geni_serial_secondary_active()
320 reg = readl(uport->membase + offset); in qcom_geni_serial_poll_bitfield()
[all …]
H A Dtimbuart.c42 u32 ier = ioread32(port->membase + TIMBUART_IER) & ~RXFLAGS; in timbuart_stop_rx()
43 iowrite32(ier, port->membase + TIMBUART_IER); in timbuart_stop_rx()
49 u32 ier = ioread32(port->membase + TIMBUART_IER) & ~TXBAE; in timbuart_stop_tx()
50 iowrite32(ier, port->membase + TIMBUART_IER); in timbuart_stop_tx()
64 u32 isr = ioread32(port->membase + TIMBUART_ISR); in timbuart_tx_empty()
72 u8 ctl = ioread8(port->membase + TIMBUART_CTRL) | in timbuart_flush_buffer()
75 iowrite8(ctl, port->membase + TIMBUART_CTRL); in timbuart_flush_buffer()
76 iowrite32(TXBF, port->membase + TIMBUART_ISR); in timbuart_flush_buffer()
84 while (ioread32(port->membase + TIMBUART_ISR) & RXDP) { in timbuart_rx_chars()
85 u8 ch = ioread8(port->membase + TIMBUART_RXFIFO); in timbuart_rx_chars()
[all …]
H A Dmeson_uart.c102 val = readl(port->membase + AML_UART_STATUS); in meson_uart_tx_empty()
111 val = readl(port->membase + AML_UART_CONTROL); in meson_uart_stop_tx()
113 writel(val, port->membase + AML_UART_CONTROL); in meson_uart_stop_tx()
120 val = readl(port->membase + AML_UART_CONTROL); in meson_uart_stop_rx()
122 writel(val, port->membase + AML_UART_CONTROL); in meson_uart_stop_rx()
134 val = readl(port->membase + AML_UART_CONTROL); in meson_uart_shutdown()
137 writel(val, port->membase + AML_UART_CONTROL); in meson_uart_shutdown()
153 while (!(readl(port->membase + AML_UART_STATUS) & AML_UART_TX_FULL)) { in meson_uart_start_tx()
155 writel(port->x_char, port->membase + AML_UART_WFIFO); in meson_uart_start_tx()
164 writel(ch, port->membase + AML_UART_WFIFO); in meson_uart_start_tx()
[all …]
H A Dfsl_linflexuart.c147 ier = readl(port->membase + LINIER); in linflex_stop_tx()
149 writel(ier, port->membase + LINIER); in linflex_stop_tx()
156 ier = readl(port->membase + LINIER); in linflex_stop_rx()
157 writel(ier & ~LINFLEXD_LINIER_DRIE, port->membase + LINIER); in linflex_stop_rx()
164 writeb(c, sport->membase + BDRL); in linflex_put_char()
167 while (((status = readl(sport->membase + UARTSR)) & in linflex_put_char()
172 writel(status | LINFLEXD_UARTSR_DTFTFF, sport->membase + UARTSR); in linflex_put_char()
197 ier = readl(port->membase + LINIER); in linflex_start_tx()
198 writel(ier | LINFLEXD_LINIER_DTIE, port->membase + LINIER); in linflex_start_tx()
236 status = readl(sport->membase + UARTSR); in linflex_rxint()
[all …]
H A Dxilinx_uartps.c250 while ((readl(port->membase + CDNS_UART_SR) & in cdns_uart_handle_rx()
253 rxbs_status = readl(port->membase + CDNS_UART_RXBS); in cdns_uart_handle_rx()
254 data = readl(port->membase + CDNS_UART_FIFO); in cdns_uart_handle_rx()
338 val = readl(cdns_uart->port->membase + CDNS_UART_MODEMCR); in cdns_rts_gpio_enable()
343 writel(val, cdns_uart->port->membase + CDNS_UART_MODEMCR); in cdns_rts_gpio_enable()
385 status = readl(port->membase + CDNS_UART_SR); in cdns_uart_tx_empty()
436 writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_IDR); in cdns_uart_handle_tx()
442 !(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXFULL) && in cdns_uart_handle_tx()
444 writel(ch, port->membase + CDNS_UART_FIFO); in cdns_uart_handle_tx()
452 writel(CDNS_UART_IXR_TXEMPTY, cdns_uart->port->membase + CDNS_UART_IER); in cdns_uart_handle_tx()
[all …]
H A Dlpc32xx_hs.c103 port->membase))) == 0) in wait_for_xmit_empty()
117 port->membase))) < 32) in wait_for_xmit_ready()
128 writel((u32)ch, LPC32XX_HSUART_FIFO(port->membase)); in lpc32xx_hsuart_console_putchar()
164 if (!port->membase) in lpc32xx_hsuart_console_setup()
240 while ((readl(LPC32XX_HSUART_LEVEL(port->membase)) > 0) && in __serial_uart_flush()
242 readl(LPC32XX_HSUART_FIFO(port->membase)); in __serial_uart_flush()
251 tmp = readl(LPC32XX_HSUART_FIFO(port->membase)); in __serial_lpc32xx_rx()
259 LPC32XX_HSUART_IIR(port->membase)); in __serial_lpc32xx_rx()
268 tmp = readl(LPC32XX_HSUART_FIFO(port->membase)); in __serial_lpc32xx_rx()
276 u32 level = readl(LPC32XX_HSUART_LEVEL(port->membase)); in serial_lpc32xx_tx_ready()
[all …]
H A Ddigicolor-usart.c85 return !!(readb_relaxed(port->membase + UA_STATUS_FIFO) & in digicolor_uart_tx_full()
91 return !!(readb_relaxed(port->membase + UA_STATUS_FIFO) & in digicolor_uart_rx_empty()
97 u8 int_enable = readb_relaxed(port->membase + UA_INT_ENABLE); in digicolor_uart_stop_tx()
100 writeb_relaxed(int_enable, port->membase + UA_INT_ENABLE); in digicolor_uart_stop_tx()
105 u8 int_enable = readb_relaxed(port->membase + UA_INT_ENABLE); in digicolor_uart_start_tx()
108 writeb_relaxed(int_enable, port->membase + UA_INT_ENABLE); in digicolor_uart_start_tx()
113 u8 int_enable = readb_relaxed(port->membase + UA_INT_ENABLE); in digicolor_uart_stop_rx()
116 writeb_relaxed(int_enable, port->membase + UA_INT_ENABLE); in digicolor_uart_stop_rx()
127 writeb_relaxed(UA_INT_RX, dp->port.membase + UA_INTFLAG_SET); in digicolor_rx_poll()
144 ch = readb_relaxed(port->membase + UA_EMI_REC); in digicolor_uart_rx()
[all …]
H A Dlantiq.c144 u32 fstat = __raw_readl(port->membase + LTQ_ASC_FSTAT); in lqasc_tx_ready()
159 writeb(ch, port->membase + LTQ_ASC_TBUF)); in lqasc_start_tx()
167 __raw_writel(ASCWHBSTATE_CLRREN, port->membase + LTQ_ASC_WHBSTATE); in lqasc_stop_rx()
176 fifocnt = __raw_readl(port->membase + LTQ_ASC_FSTAT) & in lqasc_rx_chars()
180 ch = readb(port->membase + LTQ_ASC_RBUF); in lqasc_rx_chars()
181 rsr = (__raw_readl(port->membase + LTQ_ASC_STATE) in lqasc_rx_chars()
194 port->membase + LTQ_ASC_WHBSTATE); in lqasc_rx_chars()
198 port->membase + LTQ_ASC_WHBSTATE); in lqasc_rx_chars()
203 port->membase + LTQ_ASC_WHBSTATE); in lqasc_rx_chars()
240 __raw_writel(ASC_IRNCR_TIR, port->membase + LTQ_ASC_IRNCR); in lqasc_tx_int()
[all …]
H A Dsunplus-uart.c82 writel(ch, port->membase + SUP_UART_DATA); in sp_uart_put_char()
87 unsigned int lsr = readl(port->membase + SUP_UART_LSR); in sunplus_tx_buf_not_full()
94 unsigned int lsr = readl(port->membase + SUP_UART_LSR); in sunplus_tx_empty()
101 unsigned int mcr = readl(port->membase + SUP_UART_MCR); in sunplus_set_mctrl()
128 writel(mcr, port->membase + SUP_UART_MCR); in sunplus_set_mctrl()
135 mcr = readl(port->membase + SUP_UART_MCR); in sunplus_get_mctrl()
159 isc = readl(port->membase + SUP_UART_ISC); in sunplus_stop_tx()
161 writel(isc, port->membase + SUP_UART_ISC); in sunplus_stop_tx()
168 isc = readl(port->membase + SUP_UART_ISC); in sunplus_start_tx()
170 writel(isc, port->membase + SUP_UART_ISC); in sunplus_start_tx()
[all …]
H A Dmcf.c62 return (readb(port->membase + MCFUART_USR) & MCFUART_USR_TXEMPTY) ? in mcf_tx_empty()
73 sigs = (readb(port->membase + MCFUART_UIPR) & MCFUART_UIPR_CTS) ? in mcf_get_mctrl()
91 writeb(MCFUART_UOP_RTS, port->membase + MCFUART_UOP1); in mcf_set_mctrl()
93 writeb(MCFUART_UOP_RTS, port->membase + MCFUART_UOP0); in mcf_set_mctrl()
104 writeb(MCFUART_UCR_TXENABLE, port->membase + MCFUART_UCR); in mcf_start_tx()
106 writeb(MCFUART_UOP_RTS, port->membase + MCFUART_UOP1); in mcf_start_tx()
109 writeb(pp->imr, port->membase + MCFUART_UIMR); in mcf_start_tx()
119 writeb(pp->imr, port->membase + MCFUART_UIMR); in mcf_stop_tx()
129 writeb(pp->imr, port->membase + MCFUART_UIMR); in mcf_stop_rx()
140 writeb(MCFUART_UCR_CMDBREAKSTART, port->membase + MCFUART_UCR); in mcf_break_ctl()
[all …]
H A Dfsl_lpuart.c388 return readl(port->membase + off); in lpuart32_read()
390 return ioread32be(port->membase + off); in lpuart32_read()
401 writel(val, port->membase + off); in lpuart32_write()
404 iowrite32be(val, port->membase + off); in lpuart32_write()
448 cr2 = readb(port->membase + UARTCR2); in lpuart_stop_tx()
450 writeb(cr2, port->membase + UARTCR2); in lpuart_stop_tx()
466 cr2 = readb(port->membase + UARTCR2); in lpuart_stop_rx()
467 writeb(cr2 & ~UARTCR2_RE, port->membase + UARTCR2); in lpuart_stop_rx()
621 fifo = readb(port->membase + UARTCFIFO); in lpuart_flush_buffer()
623 writeb(fifo, port->membase + UARTCFIFO); in lpuart_flush_buffer()
[all …]
H A Dliteuart.c81 litex_write8(port->membase + OFF_EV_ENABLE, uart->irq_reg); in liteuart_update_irq_reg()
104 unsigned char __iomem *membase = port->membase; in liteuart_rx_chars() local
107 while (!litex_read8(membase + OFF_RXEMPTY)) { in liteuart_rx_chars()
108 ch = litex_read8(membase + OFF_RXTX); in liteuart_rx_chars()
112 litex_write8(membase + OFF_EV_PENDING, EV_RX); in liteuart_rx_chars()
127 !litex_read8(port->membase + OFF_TXFULL), in liteuart_tx_chars()
128 litex_write8(port->membase + OFF_RXTX, ch)); in liteuart_tx_chars()
143 isr = litex_read8(port->membase + OFF_EV_PENDING) & uart->irq_reg; in liteuart_interrupt()
165 if (!litex_read8(port->membase + OFF_TXFULL)) in liteuart_tx_empty()
293 /* get membase */ in liteuart_probe()
[all …]
H A Dpch_uart.c208 void __iomem *membase; member
312 "IER: \t0x%02x\n", ioread8(priv->membase + UART_IER)); in port_show_regs()
314 "IIR: \t0x%02x\n", ioread8(priv->membase + UART_IIR)); in port_show_regs()
316 "LCR: \t0x%02x\n", ioread8(priv->membase + UART_LCR)); in port_show_regs()
318 "MCR: \t0x%02x\n", ioread8(priv->membase + UART_MCR)); in port_show_regs()
320 "LSR: \t0x%02x\n", ioread8(priv->membase + UART_LSR)); in port_show_regs()
322 "MSR: \t0x%02x\n", ioread8(priv->membase + UART_MSR)); in port_show_regs()
325 ioread8(priv->membase + PCH_UART_BRCSR)); in port_show_regs()
327 lcr = ioread8(priv->membase + UART_LCR); in port_show_regs()
328 iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR); in port_show_regs()
[all …]
H A Dmen_z135_uart.c145 reg = ioread32(port->membase + addr); in men_z135_reg_set()
147 iowrite32(reg, port->membase + addr); in men_z135_reg_set()
167 reg = ioread32(port->membase + addr); in men_z135_reg_clr()
169 iowrite32(reg, port->membase + addr); in men_z135_reg_clr()
228 stat_reg = ioread32(port->membase + MEN_Z135_STAT_REG); in get_rx_fifo_content()
271 memcpy_fromio(uart->rxbuf, port->membase + MEN_Z135_RX_RAM, room); in men_z135_handle_rx()
274 iowrite32(room, port->membase + MEN_Z135_RX_CTRL); in men_z135_handle_rx()
317 wptr = ioread32(port->membase + MEN_Z135_TX_CTRL); in men_z135_handle_tx()
347 memcpy_toio(port->membase + MEN_Z135_TX_RAM, tail, n); in men_z135_handle_tx()
349 iowrite32(n & 0x3ff, port->membase + MEN_Z135_TX_CTRL); in men_z135_handle_tx()
[all …]
/linux/drivers/net/mdio/
H A Dmdio-ipq4019.c52 void __iomem *membase; member
63 return readl_poll_timeout(priv->membase + MDIO_CMD_REG, busy, in ipq4019_mdio_wait_busy()
78 data = readl(priv->membase + MDIO_MODE_REG); in ipq4019_mdio_read_c45()
82 writel(data, priv->membase + MDIO_MODE_REG); in ipq4019_mdio_read_c45()
85 writel((mii_id << 8) | mmd, priv->membase + MDIO_ADDR_REG); in ipq4019_mdio_read_c45()
88 writel(reg, priv->membase + MDIO_DATA_WRITE_REG); in ipq4019_mdio_read_c45()
93 writel(cmd, priv->membase + MDIO_CMD_REG); in ipq4019_mdio_read_c45()
101 writel(cmd, priv->membase + MDIO_CMD_REG); in ipq4019_mdio_read_c45()
107 return readl(priv->membase + MDIO_DATA_READ_REG); in ipq4019_mdio_read_c45()
119 data = readl(priv->membase + MDIO_MODE_REG); in ipq4019_mdio_read_c22()
[all …]
/linux/drivers/gpio/
H A Dgpio-timberdale.c35 void __iomem *membase; member
50 reg = ioread32(tgpio->membase + offset); in timbgpio_update_bit()
57 iowrite32(reg, tgpio->membase + offset); in timbgpio_update_bit()
73 value = ioread32(tgpio->membase + TGPIOVAL); in timbgpio_gpio_get()
110 iowrite32(tgpio->last_ier, tgpio->membase + TGPIO_IER); in timbgpio_irq_disable()
127 iowrite32(tgpio->last_ier, tgpio->membase + TGPIO_IER); in timbgpio_irq_enable()
143 ver = ioread32(tgpio->membase + TGPIO_VER); in timbgpio_irq_type()
147 lvr = ioread32(tgpio->membase + TGPIO_LVR); in timbgpio_irq_type()
148 flr = ioread32(tgpio->membase + TGPIO_FLR); in timbgpio_irq_type()
150 bflr = ioread32(tgpio->membase + TGPIO_BFLR); in timbgpio_irq_type()
[all …]
H A Dgpio-sa1100.c19 void __iomem *membase; member
42 return readl_relaxed(sa1100_gpio_chip(chip)->membase + R_GPLR) & in sa1100_gpio_get()
51 writel_relaxed(BIT(offset), sa1100_gpio_chip(chip)->membase + reg); in sa1100_gpio_set()
58 void __iomem *gpdr = sa1100_gpio_chip(chip)->membase + R_GPDR; in sa1100_get_direction()
68 void __iomem *gpdr = sa1100_gpio_chip(chip)->membase + R_GPDR; in sa1100_direction_input()
80 void __iomem *gpdr = sa1100_gpio_chip(chip)->membase + R_GPDR; in sa1100_direction_output()
108 .membase = (void *)&GPLR,
119 void *base = sgc->membase; in sa1100_update_edge_regs()
161 writel_relaxed(BIT(d->hwirq), sgc->membase + R_GEDR); in sa1100_gpio_ack()
237 void __iomem *gedr = sgc->membase + R_GEDR; in sa1100_gpio_handler()
[all …]
/linux/drivers/clk/x86/
H A Dclk-cgu.c30 lgm_set_clk_val(ctx->membase, list->div_off, list->div_shift, in lgm_clk_register_fixed()
46 val = lgm_get_clk_val(mux->membase, mux->reg, mux->shift, in lgm_clk_mux_get_parent()
60 lgm_set_clk_val(mux->membase, mux->reg, mux->shift, in lgm_clk_mux_set_parent()
104 mux->membase = ctx->membase; in lgm_clk_register_mux()
117 lgm_set_clk_val(mux->membase, reg, shift, width, list->mux_val); in lgm_clk_register_mux()
128 val = lgm_get_clk_val(divider->membase, divider->reg, in lgm_clk_divider_recalc_rate()
158 lgm_set_clk_val(divider->membase, divider->reg, in lgm_clk_divider_set_rate()
169 lgm_set_clk_val(div->membase, div->reg, div->shift_gate, in lgm_clk_divider_enable_disable()
218 div->membase = ctx->membase; in lgm_clk_register_divider()
234 lgm_set_clk_val(div->membase, reg, shift, width, list->div_val); in lgm_clk_register_divider()
[all …]
H A Dclk-cgu-pll.c45 mult = lgm_get_clk_val(pll->membase, PLL_REF_DIV(pll->reg), 0, 12); in lgm_pll_recalc_rate()
46 div = lgm_get_clk_val(pll->membase, PLL_REF_DIV(pll->reg), 18, 6); in lgm_pll_recalc_rate()
47 frac = lgm_get_clk_val(pll->membase, pll->reg, 2, 24); in lgm_pll_recalc_rate()
60 ret = lgm_get_clk_val(pll->membase, pll->reg, 0, 1); in lgm_pll_is_enabled()
71 lgm_set_clk_val(pll->membase, pll->reg, 0, 1, 1); in lgm_pll_enable()
72 ret = regmap_read_poll_timeout_atomic(pll->membase, pll->reg, in lgm_pll_enable()
83 lgm_set_clk_val(pll->membase, pll->reg, 0, 1, 0); in lgm_pll_disable()
113 pll->membase = ctx->membase; in lgm_clk_register_pll()
/linux/drivers/tty/serial/8250/
H A D8250_pci1xxxx.c154 void __iomem *membase; member
167 writel(UART_SYSLOCK, port->membase + UART_SYSLOCK_REG); in pci1xxxx_set_sys_lock()
168 return readl(port->membase + UART_SYSLOCK_REG); in pci1xxxx_set_sys_lock()
183 writel(0x0, port->membase + UART_SYSLOCK_REG); in pci1xxxx_release_sys_lock()
262 writel(UART_BIT_DIVISOR_8, port->membase + FRAC_DIV_CFG_REG); in pci1xxxx_set_divisor()
264 writel(UART_BIT_DIVISOR_16, port->membase + FRAC_DIV_CFG_REG); in pci1xxxx_set_divisor()
267 port->membase + UART_BAUD_CLK_DIVISOR_REG); in pci1xxxx_set_divisor()
277 adcl_cfg_reg = readl(port->membase + ADCL_CFG_REG); in pci1xxxx_set_mctrl()
283 modem_ctl_reg = readl(port->membase + UART_MODEM_CTL_REG); in pci1xxxx_set_mctrl()
288 line_stat_reg = readl(port->membase + UART_LINE_STAT_REG); in pci1xxxx_set_mctrl()
[all …]
H A D8250_uniphier.c43 if (!device->port.membase) in uniphier_early_console_setup()
92 return (readl(p->membase + offset) >> valshift) & 0xff; in uniphier_serial_in()
123 writel(value, p->membase + offset); in uniphier_serial_out()
135 tmp = readl(p->membase + offset); in uniphier_serial_out()
138 writel(tmp, p->membase + offset); in uniphier_serial_out()
150 return readl(up->port.membase + UNIPHIER_UART_DLR); in uniphier_serial_dl_read()
155 writel(value, up->port.membase + UNIPHIER_UART_DLR); in uniphier_serial_dl_write()
164 void __iomem *membase; in uniphier_uart_probe() local
173 membase = devm_ioremap(dev, regs->start, resource_size(regs)); in uniphier_uart_probe()
174 if (!membase) in uniphier_uart_probe()
[all …]
/linux/drivers/i2c/busses/
H A Di2c-uniphier-f.c81 void __iomem *membase; member
109 writel(*priv->buf++, priv->membase + UNIPHIER_FI2C_DTTX); in uniphier_fi2c_fill_txfifo()
123 *priv->buf++ = readl(priv->membase + UNIPHIER_FI2C_DTRX); in uniphier_fi2c_drain_rxfifo()
130 writel(priv->enabled_irqs, priv->membase + UNIPHIER_FI2C_IE); in uniphier_fi2c_set_irqs()
136 writel(mask, priv->membase + UNIPHIER_FI2C_IC); in uniphier_fi2c_clear_irqs()
144 priv->membase + UNIPHIER_FI2C_CR); in uniphier_fi2c_stop()
154 irq_status = readl(priv->membase + UNIPHIER_FI2C_INT); in uniphier_fi2c_interrupt()
213 priv->membase + UNIPHIER_FI2C_CR); in uniphier_fi2c_interrupt()
254 writel(0, priv->membase + UNIPHIER_FI2C_TBC); in uniphier_fi2c_tx_init()
257 priv->membase + UNIPHIER_FI2C_DTTX); in uniphier_fi2c_tx_init()
[all …]
/linux/drivers/atm/
H A Didt77252.h355 void __iomem *membase; /* SAR's memory base address */ member
441 #define SAR_REG_DR0 (card->membase + 0x00)
442 #define SAR_REG_DR1 (card->membase + 0x04)
443 #define SAR_REG_DR2 (card->membase + 0x08)
444 #define SAR_REG_DR3 (card->membase + 0x0C)
445 #define SAR_REG_CMD (card->membase + 0x10)
446 #define SAR_REG_CFG (card->membase + 0x14)
447 #define SAR_REG_STAT (card->membase + 0x18)
448 #define SAR_REG_RSQB (card->membase + 0x1C)
449 #define SAR_REG_RSQT (card->membase + 0x20)
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/linux/drivers/input/keyboard/
H A Dlocomokbd.c72 static inline void locomokbd_charge_all(unsigned long membase) in locomokbd_charge_all() argument
74 locomo_writel(0x00FF, membase + LOCOMO_KSC); in locomokbd_charge_all()
77 static inline void locomokbd_activate_all(unsigned long membase) in locomokbd_activate_all() argument
81 locomo_writel(0, membase + LOCOMO_KSC); in locomokbd_activate_all()
82 r = locomo_readl(membase + LOCOMO_KIC); in locomokbd_activate_all()
84 locomo_writel(r, membase + LOCOMO_KIC); in locomokbd_activate_all()
87 static inline void locomokbd_activate_col(unsigned long membase, int col) in locomokbd_activate_col() argument
94 locomo_writel(nbset, membase + LOCOMO_KSC); in locomokbd_activate_col()
97 static inline void locomokbd_reset_col(unsigned long membase, int col) in locomokbd_reset_col() argument
102 locomo_writel(nbset, membase + LOCOMO_KSC); in locomokbd_reset_col()
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