Lines Matching full:membase
388 return readl(port->membase + off); in lpuart32_read()
390 return ioread32be(port->membase + off); in lpuart32_read()
401 writel(val, port->membase + off); in lpuart32_write()
404 iowrite32be(val, port->membase + off); in lpuart32_write()
448 cr2 = readb(port->membase + UARTCR2); in lpuart_stop_tx()
450 writeb(cr2, port->membase + UARTCR2); in lpuart_stop_tx()
466 cr2 = readb(port->membase + UARTCR2); in lpuart_stop_rx()
467 writeb(cr2 & ~UARTCR2_RE, port->membase + UARTCR2); in lpuart_stop_rx()
621 fifo = readb(port->membase + UARTCFIFO); in lpuart_flush_buffer()
623 writeb(fifo, port->membase + UARTCFIFO); in lpuart_flush_buffer()
630 while (!(readb(port->membase + offset) & bit)) in lpuart_wait_bit_set()
652 writeb(0, port->membase + UARTCR2); in lpuart_poll_init()
654 fifo = readb(port->membase + UARTPFIFO); in lpuart_poll_init()
657 port->membase + UARTPFIFO); in lpuart_poll_init()
661 port->membase + UARTCFIFO); in lpuart_poll_init()
664 if (readb(port->membase + UARTSR1) & UARTSR1_RDRF) { in lpuart_poll_init()
665 readb(port->membase + UARTDR); in lpuart_poll_init()
666 writeb(UARTSFIFO_RXUF, port->membase + UARTSFIFO); in lpuart_poll_init()
669 writeb(0, port->membase + UARTTWFIFO); in lpuart_poll_init()
670 writeb(1, port->membase + UARTRWFIFO); in lpuart_poll_init()
673 writeb(UARTCR2_RE | UARTCR2_TE, port->membase + UARTCR2); in lpuart_poll_init()
683 writeb(c, port->membase + UARTDR); in lpuart_poll_put_char()
688 if (!(readb(port->membase + UARTSR1) & UARTSR1_RDRF)) in lpuart_poll_get_char()
691 return readb(port->membase + UARTDR); in lpuart_poll_get_char()
748 readb(port->membase + UARTTCFIFO) < sport->txfifo_size, in lpuart_transmit_buffer()
749 writeb(ch, port->membase + UARTDR)); in lpuart_transmit_buffer()
794 cr2 = readb(port->membase + UARTCR2); in lpuart_start_tx()
795 writeb(cr2 | UARTCR2_TIE, port->membase + UARTCR2); in lpuart_start_tx()
801 if (readb(port->membase + UARTSR1) & UARTSR1_TDRE) in lpuart_start_tx()
842 u8 sr1 = readb(port->membase + UARTSR1); in lpuart_tx_empty()
843 u8 sfifo = readb(port->membase + UARTSFIFO); in lpuart_tx_empty()
891 while (!(readb(sport->port.membase + UARTSFIFO) & UARTSFIFO_RXEMPT)) { in lpuart_rxint()
898 sr = readb(sport->port.membase + UARTSR1); in lpuart_rxint()
899 rx = readb(sport->port.membase + UARTDR); in lpuart_rxint()
944 writeb(UARTCFIFO_RXFLUSH, sport->port.membase + UARTCFIFO); in lpuart_rxint()
945 writeb(UARTSFIFO_RXOF, sport->port.membase + UARTSFIFO); in lpuart_rxint()
1044 sts = readb(sport->port.membase + UARTSR1); in lpuart_int()
1048 readb(sport->port.membase + UARTDR); in lpuart_int()
1051 writeb(UARTCFIFO_RXFLUSH, sport->port.membase + UARTCFIFO); in lpuart_int()
1128 u8 sr = readb(sport->port.membase + UARTSR1); in lpuart_copy_rx_to_tty()
1134 cr2 = readb(sport->port.membase + UARTCR2); in lpuart_copy_rx_to_tty()
1136 writeb(cr2, sport->port.membase + UARTCR2); in lpuart_copy_rx_to_tty()
1139 readb(sport->port.membase + UARTDR); in lpuart_copy_rx_to_tty()
1154 if (readb(sport->port.membase + UARTSFIFO) & in lpuart_copy_rx_to_tty()
1157 sport->port.membase + UARTSFIFO); in lpuart_copy_rx_to_tty()
1159 sport->port.membase + UARTCFIFO); in lpuart_copy_rx_to_tty()
1163 writeb(cr2, sport->port.membase + UARTCR2); in lpuart_copy_rx_to_tty()
1424 writeb(readb(sport->port.membase + UARTCR5) | UARTCR5_RDMAS, in lpuart_start_rx_dma()
1425 sport->port.membase + UARTCR5); in lpuart_start_rx_dma()
1452 u8 modem = readb(port->membase + UARTMODEM) & in lpuart_config_rs485()
1454 writeb(modem, port->membase + UARTMODEM); in lpuart_config_rs485()
1472 writeb(modem, port->membase + UARTMODEM); in lpuart_config_rs485()
1525 cr1 = readb(port->membase + UARTCR1); in lpuart_get_mctrl()
1548 cr1 = readb(port->membase + UARTCR1); in lpuart_set_mctrl()
1555 writeb(cr1, port->membase + UARTCR1); in lpuart_set_mctrl()
1576 cr2 = readb(port->membase + UARTCR2) & ~UARTCR2_SBK; in lpuart_break_ctl()
1581 writeb(cr2, port->membase + UARTCR2); in lpuart_break_ctl()
1622 cr2 = readb(sport->port.membase + UARTCR2); in lpuart_setup_watermark()
1626 writeb(cr2, sport->port.membase + UARTCR2); in lpuart_setup_watermark()
1628 fifo = readb(sport->port.membase + UARTPFIFO); in lpuart_setup_watermark()
1630 sport->port.membase + UARTPFIFO); in lpuart_setup_watermark()
1634 sport->port.membase + UARTCFIFO); in lpuart_setup_watermark()
1637 if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) { in lpuart_setup_watermark()
1638 readb(sport->port.membase + UARTDR); in lpuart_setup_watermark()
1639 writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO); in lpuart_setup_watermark()
1644 writeb(0, sport->port.membase + UARTTWFIFO); in lpuart_setup_watermark()
1645 writeb(sport->rx_watermark, sport->port.membase + UARTRWFIFO); in lpuart_setup_watermark()
1648 writeb(cr2_saved, sport->port.membase + UARTCR2); in lpuart_setup_watermark()
1657 cr2 = readb(sport->port.membase + UARTCR2); in lpuart_setup_watermark_enable()
1659 writeb(cr2, sport->port.membase + UARTCR2); in lpuart_setup_watermark_enable()
1760 writeb(readb(sport->port.membase + UARTCR5) | in lpuart_tx_dma_startup()
1761 UARTCR5_TDMAS, sport->port.membase + UARTCR5); in lpuart_tx_dma_startup()
1795 cr3 = readb(sport->port.membase + UARTCR3); in lpuart_rx_dma_startup()
1797 writeb(cr3, sport->port.membase + UARTCR3); in lpuart_rx_dma_startup()
1826 fifo = readb(port->membase + UARTPFIFO); in lpuart_startup()
1943 cr2 = readb(port->membase + UARTCR2); in lpuart_shutdown()
1946 writeb(cr2, port->membase + UARTCR2); in lpuart_shutdown()
1998 cr1 = old_cr1 = readb(port->membase + UARTCR1); in lpuart_set_termios()
1999 old_cr2 = readb(port->membase + UARTCR2); in lpuart_set_termios()
2000 cr3 = readb(port->membase + UARTCR3); in lpuart_set_termios()
2001 cr4 = readb(port->membase + UARTCR4); in lpuart_set_termios()
2002 bdh = readb(port->membase + UARTBDH); in lpuart_set_termios()
2003 modem = readb(port->membase + UARTMODEM); in lpuart_set_termios()
2112 port->membase + UARTCR2); in lpuart_set_termios()
2120 writeb(cr4 | brfa, port->membase + UARTCR4); in lpuart_set_termios()
2121 writeb(bdh, port->membase + UARTBDH); in lpuart_set_termios()
2122 writeb(sbr & 0xFF, port->membase + UARTBDL); in lpuart_set_termios()
2123 writeb(cr3, port->membase + UARTCR3); in lpuart_set_termios()
2124 writeb(cr1, port->membase + UARTCR1); in lpuart_set_termios()
2125 writeb(modem, port->membase + UARTMODEM); in lpuart_set_termios()
2128 writeb(old_cr2, port->membase + UARTCR2); in lpuart_set_termios()
2487 writeb(ch, port->membase + UARTDR); in lpuart_console_putchar()
2510 cr2 = old_cr2 = readb(sport->port.membase + UARTCR2); in lpuart_console_write()
2513 writeb(cr2, sport->port.membase + UARTCR2); in lpuart_console_write()
2520 writeb(old_cr2, sport->port.membase + UARTCR2); in lpuart_console_write()
2567 cr = readb(sport->port.membase + UARTCR2); in lpuart_console_get_options()
2574 cr = readb(sport->port.membase + UARTCR1); in lpuart_console_get_options()
2589 bdh = readb(sport->port.membase + UARTBDH); in lpuart_console_get_options()
2591 bdl = readb(sport->port.membase + UARTBDL); in lpuart_console_get_options()
2595 brfa = readb(sport->port.membase + UARTCR4); in lpuart_console_get_options()
2729 if (!device->port.membase) in lpuart_early_console_setup()
2739 if (!device->port.membase) in lpuart32_early_console_setup()
2754 if (!device->port.membase) in ls1028a_early_console_setup()
2776 if (!device->port.membase) in lpuart32_imx_early_console_setup()
2780 device->port.membase += IMX_REG_OFF; in lpuart32_imx_early_console_setup()
2846 global_addr = port->membase + UART_GLOBAL - IMX_REG_OFF; in lpuart_global_reset()
2876 sport->port.membase = devm_platform_get_and_ioremap_resource(pdev, 0, &res); in lpuart_probe()
2877 if (IS_ERR(sport->port.membase)) in lpuart_probe()
2878 return PTR_ERR(sport->port.membase); in lpuart_probe()
2880 sport->port.membase += sdata->reg_off; in lpuart_probe()
3044 val = readb(sport->port.membase + UARTCR2); in serial_lpuart_enable_wakeup()
3049 writeb(val, sport->port.membase + UARTCR2); in serial_lpuart_enable_wakeup()
3124 temp = readb(sport->port.membase + UARTCR2); in lpuart_suspend()
3126 writeb(temp, sport->port.membase + UARTCR2); in lpuart_suspend()
3147 writeb(readb(sport->port.membase + UARTCR5) & in lpuart_suspend()
3148 ~UARTCR5_RDMAS, sport->port.membase + UARTCR5); in lpuart_suspend()
3160 temp = readb(sport->port.membase + UARTCR5); in lpuart_suspend()
3162 writeb(temp, sport->port.membase + UARTCR5); in lpuart_suspend()