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/linux/Documentation/devicetree/bindings/display/mediatek/
H A Dmediatek,split.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/mediatek/mediatek,split.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Mediatek display split
10 - Chun-Kuang Hu <chunkuang.hu@kernel.org>
11 - Philipp Zabel <p.zabel@pengutronix.de>
14 Mediatek display split, namely SPLIT, is used to split stream to two
18 Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
24 - enum:
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H A Dmediatek,dp.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/mediatek/mediatek,dp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek Display Port Controller
10 - Chun-Kuang Hu <chunkuang.hu@kernel.org>
11 - Jitao shi <jitao.shi@mediatek.com>
14 MediaTek DP and eDP are different hardwares and there are some features
24 - mediatek,mt8188-dp-tx
25 - mediatek,mt8188-edp-tx
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H A Dmediatek,dpi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/mediatek/mediatek,dpi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek DPI and DP_INTF Controller
10 - CK Hu <ck.hu@mediatek.com>
11 - Jitao shi <jitao.shi@mediatek.com>
14 The MediaTek DPI and DP_INTF function blocks are a sink of the display
15 subsystem and provides 8-bit RGB/YUV444 or 8/10/10-bit YUV422 pixel data on a
21 - enum:
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H A Dmediatek,padding.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/mediatek/mediatek,padding.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek Display Padding
10 - Chun-Kuang Hu <chunkuang.hu@kernel.org>
11 - Philipp Zabel <p.zabel@pengutronix.de>
16 width of a layer to be 2-pixel-align, or 4-pixel-align when ETHDR is enabled,
24 - mediatek,mt8188-disp-padding
25 - mediatek,mt8195-mdp3-padding
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H A Dmediatek,cec.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/mediatek/mediatek,cec.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Mediatek HDMI CEC Controller
10 - CK Hu <ck.hu@mediatek.com>
11 - Jitao shi <jitao.shi@mediatek.com>
19 - mediatek,mt7623-cec
20 - mediatek,mt8167-cec
21 - mediatek,mt8173-cec
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H A Dmediatek,hdmi-ddc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/mediatek/mediatek,hdmi-ddc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Mediatek HDMI DDC
10 - CK Hu <ck.hu@mediatek.com>
11 - Jitao shi <jitao.shi@mediatek.com>
19 - mediatek,mt7623-hdmi-ddc
20 - mediatek,mt8167-hdmi-ddc
21 - mediatek,mt8173-hdmi-ddc
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H A Dmediatek,wdma.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/mediatek/mediatek,wdma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Mediatek Write Direct Memory Access
10 - Chun-Kuang Hu <chunkuang.hu@kernel.org>
11 - Philipp Zabel <p.zabel@pengutronix.de>
14 Mediatek Write Direct Memory Access(WDMA) component used to write
18 Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
24 - enum:
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H A Dmediatek,hdmi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/mediatek/mediatek,hdmi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Mediatek HDMI Encoder
10 - CK Hu <ck.hu@mediatek.com>
11 - Jitao shi <jitao.shi@mediatek.com>
14 The Mediatek HDMI encoder can generate HDMI 1.4a or MHL 2.0 signals from
20 - mediatek,mt2701-hdmi
21 - mediatek,mt7623-hdmi
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/linux/Documentation/devicetree/bindings/media/
H A Dmediatek,mdp3-tcc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/mediatek,mdp3-tcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek Media Data Path 3 Tone Curve Conversion
10 - Matthias Brugger <matthias.bgg@gmail.com>
16 brightness range that standard display devices typically support.
21 - mediatek,mt8195-mdp3-tcc
26 mediatek,gce-client-reg:
28 The register of display function block to be set by gce. There are 4 arguments,
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H A Dmediatek,mdp3-tdshp.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/mediatek,mdp3-tdshp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek Media Data Path 3 Two-Dimensional Sharpness
10 - Matthias Brugger <matthias.bgg@gmail.com>
11 - Moudy Ho <moudy.ho@mediatek.com>
14 Two-Dimensional Sharpness (TDSHP) is a Media Profile Path 3 (MDP3) component
20 - mediatek,mt8195-mdp3-tdshp
25 mediatek,gce-client-reg:
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H A Dmediatek,mdp3-fg.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/mediatek,mdp3-fg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek Media Data Path 3 Film Grain
10 - Matthias Brugger <matthias.bgg@gmail.com>
11 - Moudy Ho <moudy.ho@mediatek.com>
20 - mediatek,mt8195-mdp3-fg
25 mediatek,gce-client-reg:
27 The register of display function block to be set by gce. There are 4 arguments,
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H A Dmediatek,mdp3-hdr.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/mediatek,mdp3-hdr.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek Media Data Path 3 HDR
10 - Matthias Brugger <matthias.bgg@gmail.com>
11 - Moudy Ho <moudy.ho@mediatek.com>
20 - mediatek,mt8195-mdp3-hdr
25 mediatek,gce-client-reg:
27 The register of display function block to be set by gce. There are 4 arguments,
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H A Dmediatek,mdp3-stitch.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/mediatek,mdp3-stitch.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek Media Data Path 3 STITCH
10 - Matthias Brugger <matthias.bgg@gmail.com>
11 - Moudy Ho <moudy.ho@mediatek.com>
20 - mediatek,mt8195-mdp3-stitch
25 mediatek,gce-client-reg:
27 The register of display function block to be set by gce. There are 4 arguments,
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/linux/drivers/gpu/drm/ci/
H A Dtest.yml1 .test-rules:
3 - if: '$FD_FARM == "offline" && $RUNNER_TAG =~ /^google-freedreno-/'
5 - if: '$COLLABORA_FARM == "offline" && $RUNNER_TAG =~ /^mesa-ci-x86-64-lava-/'
7 - !reference [.no_scheduled_pipelines-rules, rules]
8 - when: on_success
10 .lava-test:
12 - .test-rules
16 - rm -rf install
17 - tar -xf artifacts/install.tar
18 - mv install/* artifacts/.
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/linux/drivers/gpu/drm/mediatek/
H A Dmtk_drm_drv.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2015 MediaTek Inc.
4 * Author: YT SHEN <yt.shen@mediatek.com>
13 #include <linux/dma-mapping.h>
34 #define DRIVER_NAME "mediatek"
35 #define DRIVER_DESC "Mediatek SoC DRM"
50 if (info->num_planes != 1) in mtk_drm_mode_fb_create()
51 return ERR_PTR(-EINVAL); in mtk_drm_mode_fb_create()
326 .min_width = 2, /* 2-pixel align when ethdr is bypassed */
331 { .compatible = "mediatek,mt2701-mmsys",
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H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 tristate "DRM Support for Mediatek SoCs"
19 Choose this option if you have a Mediatek SoCs.
20 The module will be called mediatek-drm
25 tristate "DRM DPTX Support for MediaTek SoCs"
31 DRM/KMS Display Port driver for MediaTek SoCs.
34 tristate "DRM HDMI Support for Mediatek SoCs"
38 DRM/KMS HDMI driver for Mediatek SoCs
/linux/Documentation/devicetree/bindings/iommu/
H A Dmediatek,iommu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iommu/mediatek,iommu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek IOMMU Architecture Implementation
10 - Yong Wu <yong.wu@mediatek.com>
13 Some MediaTek SOCs contain a Multimedia Memory Management Unit (M4U), and
16 ARM Short-Descriptor translation table format for address translation.
24 +--------+
26 gals0-rx gals1-rx (Global Async Local Sync rx)
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/linux/Documentation/admin-guide/media/
H A Dplatform-cardlist.rst1 .. SPDX-License-Identifier: GPL-2.0
17 am437x-vpfe TI AM437x VPFE
18 aspeed-video Aspeed AST2400 and AST2500
19 atmel-isc ATMEL Image Sensor Controller (ISC)
20 atmel-isi ATMEL Image Sensor Interface (ISI)
24 cdns-csi2rx Cadence MIPI-CSI2 RX Controller
25 cdns-csi2tx Cadence MIPI-CSI2 TX Controller
26 coda-vpu Chips&Media Coda multi-standard codec IP
29 exynos-fimc-is EXYNOS4x12 FIMC-IS (Imaging Subsystem)
30 exynos-fimc-lite EXYNOS FIMC-LITE camera interface
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/linux/Documentation/devicetree/bindings/mailbox/
H A Dmediatek,gce-mailbox.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mailbox/mediatek,gce-mailbox.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Mediatek Global Command Engine Mailbox
10 - Houlong Wei <houlong.wei@mediatek.com>
14 critical time limitation, such as updating display configuration during the
20 - enum:
21 - mediatek,mt6779-gce
22 - mediatek,mt8173-gce
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/linux/Documentation/devicetree/bindings/phy/
H A Dmediatek,dsi-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (c) 2020 MediaTek
4 ---
5 $id: http://devicetree.org/schemas/phy/mediatek,dsi-phy.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: MediaTek MIPI Display Serial Interface (DSI) PHY
11 - Chun-Kuang Hu <chunkuang.hu@kernel.org>
12 - Philipp Zabel <p.zabel@pengutronix.de>
13 - Chunfeng Yun <chunfeng.yun@mediatek.com>
15 description: The MIPI DSI PHY supports up to 4-lane output.
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/linux/Documentation/devicetree/bindings/soc/mediatek/
H A Dmediatek,mutex.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/mediatek/mediatek,mutex.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Mediatek mutex
10 - Chun-Kuang Hu <chunkuang.hu@kernel.org>
11 - Philipp Zabel <p.zabel@pengutronix.de>
14 Mediatek mutex, namely MUTEX, is used to send the triggers signals called
15 Start Of Frame (SOF) / End Of Frame (EOF) to each sub-modules on the display
21 Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
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/linux/Documentation/devicetree/bindings/sound/
H A Dmt8195-mt6359.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/mt8195-mt6359.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek MT8195 ASoC sound card driver
10 - Trevor Wu <trevor.wu@mediatek.com>
16 - $ref: sound-card-common.yaml#
21 - mediatek,mt8195_mt6359_rt1019_rt5682
22 - mediatek,mt8195_mt6359_rt1011_rt5682
23 - mediatek,mt8195_mt6359_max98390_rt5682
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/linux/drivers/pwm/
H A Dpwm-mtk-disp.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * MediaTek display pulse-width-modulation controller driver.
4 * Copyright (c) 2015 MediaTek Inc.
5 * Author: YH Huang <yh.huang@mediatek.com>
25 #define PWM_PERIOD_MASK ((1 << PWM_PERIOD_BIT_WIDTH) - 1)
60 void __iomem *address = mdp->base + offset; in mtk_disp_pwm_update_bits()
77 if (state->polarity != PWM_POLARITY_NORMAL) in mtk_disp_pwm_apply()
78 return -EINVAL; in mtk_disp_pwm_apply()
80 if (!state->enabled && mdp->enabled) { in mtk_disp_pwm_apply()
82 mdp->data->enable_mask, 0x0); in mtk_disp_pwm_apply()
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/linux/drivers/media/platform/mediatek/vcodec/decoder/
H A Dvdec_vpu_if.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2016 MediaTek Inc.
4 * Author: PC Chen <pc.chen@mediatek.com>
13 * struct vdec_vpu_inst - VPU instance for video codec
23 * @signaled : 1 - Host has received ack message from VPU, 0 - not received
49 * vpu_dec_init - init decoder instance and allocate required resource in VPU.
56 * vpu_dec_start - start decoding, basically the function will be invoked once
66 * vpu_dec_end - end decoding, basically the function will be invoked once
69 * and check if there is a new decoded frame available to display.
76 * vpu_dec_deinit - deinit decoder instance and resource freed in VPU.
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/linux/drivers/regulator/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
38 managed regulators and simple non-configurable regulators.
64 the netlink mechanism. User-space applications can subscribe to these events
65 for real-time updates on various regulator events.
75 They provide two I2C-controlled DC/DC step-down converters with
101 tristate "Active-semi act8865 voltage regulator"
106 This driver controls a active-semi act8865 voltage output
110 tristate "Active-semi ACT8945A voltage regulator"
113 This driver controls a active-semi ACT8945A voltage regulator
114 via I2C bus. The ACT8945A features three step-down DC/DC converters
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