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/linux/drivers/pinctrl/mvebu/
H A Dpinctrl-ac5.c1 // SPDX-License-Identifier: GPL-2.0-or-later
17 #include "pinctrl-mvebu.h"
21 MPP_FUNCTION(0, "gpio", NULL),
25 MPP_FUNCTION(0, "gpio", NULL),
29 MPP_FUNCTION(0, "gpio", NULL),
33 MPP_FUNCTION(0, "gpio", NULL),
37 MPP_FUNCTION(0, "gpio", NULL),
43 MPP_FUNCTION(0, "gpio", NULL),
49 MPP_FUNCTION(0, "gpio", NULL),
54 MPP_FUNCTION(0, "gpio", NULL),
[all …]
H A Dpinctrl-armada-cp110.c1 // SPDX-License-Identifier: GPL-2.0-or-later
19 #include "pinctrl-mvebu.h"
24 * - In Armada7K (single CP) almost all the MPPs are available (except the
26 * - In Armada8K (dual CP) the MPPs are split into 2 parts, MPPs 0-31 from
27 * CPS, and MPPs 32-62 from CPM, the below flags (V_ARMADA_8K_CPM,
42 MPP_FUNCTION(0, "gpio", NULL),
51 MPP_FUNCTION(10, "ge", "mdio")),
53 MPP_FUNCTION(0, "gpio", NULL),
64 MPP_FUNCTION(0, "gpio", NULL),
76 MPP_FUNCTION(0, "gpio", NULL),
[all …]
/linux/Documentation/devicetree/bindings/net/
H A Dmdio-gpio.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/mdio-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MDIO on GPIOs
10 - Andrew Lunn <andrew@lunn.ch>
11 - Heiner Kallweit <hkallweit1@gmail.com>
12 - Russell King <linux@armlinux.org.uk>
15 - $ref: mdio.yaml#
20 - virtual,mdio-gpio
[all …]
H A Drealtek,rtl9301-switch.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/realtek,rtl9301-switch.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chris Packham <chris.packham@alliedtelesis.co.nz>
17 $ref: ethernet-switch.yaml#/$defs/ethernet-ports
22 - enum:
23 - realtek,rtl9301-switch
24 - realtek,rtl9302b-switch
25 - realtek,rtl9302c-switch
[all …]
H A Dmdio.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/mdio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MDIO Bus Common Properties
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Heiner Kallweit <hkallweit1@gmail.com>
15 These are generic properties that can apply to any MDIO bus. Any
16 MDIO bus must have a list of child nodes, one per device on the
[all …]
/linux/Documentation/devicetree/bindings/net/dsa/
H A Dqca8k.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - John Crispin <john@phrozen.org>
13 If the QCA8K switch is connect to an SoC's external mdio-bus, each subnode
16 ID. To declare the internal mdio-bus configuration, declare an MDIO node in
18 PHY it is connected to. In this config, an internal mdio-bus is registered and
19 the MDIO master is used for communication. Mixed external and internal
20 mdio-bus configurations are not supported by the hardware.
27 - enum:
[all …]
H A Dmediatek,mt7530.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Arınç ÜNAL <arinc.unal@arinc9.com>
11 - Landen Chao <Landen.Chao@mediatek.com>
12 - DENG Qingfang <dqfext@gmail.com>
13 - Sean Wang <sean.wang@mediatek.com>
14 - Daniel Golle <daniel@makrotopia.org>
17 There are three versions of MT7530, standalone, in a multi-chip module and
18 built-into a SoC.
[all …]
/linux/drivers/net/mdio/
H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 # Makefile for Linux MDIO bus drivers
4 obj-$(CONFIG_ACPI_MDIO) += acpi_mdio.o
5 obj-$(CONFIG_FWNODE_MDIO) += fwnode_mdio.o
6 obj-$(CONFIG_OF_MDIO) += of_mdio.o
8 obj-$(CONFIG_MDIO_AIROHA) += mdio-airoha.o
9 obj-$(CONFIG_MDIO_ASPEED) += mdio-aspeed.o
10 obj-$(CONFIG_MDIO_BCM_IPROC) += mdio-bcm-iproc.o
11 obj-$(CONFIG_MDIO_BCM_UNIMAC) += mdio-bcm-unimac.o
12 obj-$(CONFIG_MDIO_BITBANG) += mdio-bitbang.o
[all …]
H A Dmdio-mux-gpio.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/gpio/consumer.h>
8 #include <linux/mdio-mux.h>
15 #define DRV_DESCRIPTION "GPIO controlled MDIO bus multiplexer driver"
33 gpiod_multi_set_value_cansleep(s->gpios, values); in mdio_mux_gpio_switch_fn()
44 gpios = devm_gpiod_get_array(&pdev->dev, NULL, GPIOD_OUT_LOW); in mdio_mux_gpio_probe()
48 s = devm_kzalloc(&pdev->dev, sizeof(*s), GFP_KERNEL); in mdio_mux_gpio_probe()
50 return -ENOMEM; in mdio_mux_gpio_probe()
52 s->gpios = gpios; in mdio_mux_gpio_probe()
54 r = mdio_mux_init(&pdev->dev, pdev->dev.of_node, in mdio_mux_gpio_probe()
[all …]
/linux/arch/arm/boot/dts/nxp/vf/
H A Dvf610-zii-dev-rev-c.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 /dts-v1/;
7 #include "vf610-zii-dev.dtsi"
11 compatible = "zii,vf610dev-c", "zii,vf610dev", "fsl,vf610";
13 mdio-mux {
14 compatible = "mdio-mux-gpio";
15 pinctrl-0 = <&pinctrl_mdio_mux>;
16 pinctrl-names = "default";
20 mdio-parent-bus = <&mdio1>;
21 #address-cells = <1>;
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dfsl-ls208xa.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Freescale Layerscape-2080A family SoC.
6 * Copyright 2017-2020 NXP
12 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
13 #include <dt-bindings/thermal/thermal.h>
14 #include <dt-bindings/interrupt-controller/arm-gic.h>
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
32 #address-cells = <1>;
[all …]
H A Dfsl-lx2160a.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 // Device Tree Include file for Layerscape-LX2160A family SoC.
5 // Copyright 2018-2020 NXP
7 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/thermal/thermal.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
[all …]
/linux/arch/riscv/boot/dts/sophgo/
H A Dcv180x.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 #include <dt-bindings/clock/sophgo,cv1800.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include "cv18xx-reset.h"
13 #address-cells = <1>;
14 #size-cells = <1>;
17 compatible = "fixed-clock";
18 clock-output-names = "osc_25m";
19 #clock-cells = <0>;
[all …]
/linux/Documentation/devicetree/bindings/pinctrl/
H A Dmediatek,mt7620-pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt7620-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Arınç ÜNAL <arinc.unal@arinc9.com>
11 - Sergio Paracuellos <sergio.paracuellos@gmail.com>
20 const: ralink,mt7620-pinctrl
23 '-pins$':
28 '^(.*-)?pinmux$':
31 $ref: pinmux-node.yaml#
[all …]
H A Dralink,rt305x-pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/ralink,rt305x-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Arınç ÜNAL <arinc.unal@arinc9.com>
11 - Sergio Paracuellos <sergio.paracuellos@gmail.com>
20 const: ralink,rt305x-pinctrl
23 '-pins$':
28 '^(.*-)?pinmux$':
31 $ref: pinmux-node.yaml#
[all …]
H A Dralink,rt3352-pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/ralink,rt3352-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Arınç ÜNAL <arinc.unal@arinc9.com>
11 - Sergio Paracuellos <sergio.paracuellos@gmail.com>
20 const: ralink,rt3352-pinctrl
23 '-pins$':
28 '^(.*-)?pinmux$':
31 $ref: pinmux-node.yaml#
[all …]
H A Dralink,rt3883-pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/ralink,rt3883-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Arınç ÜNAL <arinc.unal@arinc9.com>
11 - Sergio Paracuellos <sergio.paracuellos@gmail.com>
20 const: ralink,rt3883-pinctrl
23 '-pins$':
28 '^(.*-)?pinmux$':
31 $ref: pinmux-node.yaml#
[all …]
/linux/Documentation/devicetree/bindings/mfd/
H A Dmscc,ocelot.yaml1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Ocelot Externally-Controlled Ethernet Switch
10 - Colin Foster <colin.foster@in-advantage.com>
18 The switch family is a multi-port networking switch that supports many
19 interfaces. Additionally, the device can perform pin control, MDIO buses, and
20 external GPIO expanders.
25 - mscc,vsc7512
30 "#address-cells":
[all …]
H A Dairoha,en7581-gpio-sysctl.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mfd/airoha,en7581-gpio-sysctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Airoha EN7581 GPIO System Controller
10 - Christian Marangi <ansuelsmth@gmail.com>
11 - Lorenzo Bianconi <lorenzo@kernel.org>
14 Airoha EN7581 SoC GPIO system controller which provided a register map
15 for controlling the GPIO, pins and PWM of the SoC.
20 - const: airoha,en7581-gpio-sysctl
[all …]
/linux/drivers/pinctrl/
H A Dpinctrl-xway.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/drivers/pinctrl/pinmux-xway.c
4 * based on linux/drivers/pinctrl/pinmux-pxa910.c
11 #include <linux/gpio/driver.h>
21 #include "pinctrl-lantiq.h"
110 /* --------- ase related code --------- */
115 MFP_XWAY(GPIO0, GPIO, EXIN, MII, TDM),
116 MFP_XWAY(GPIO1, GPIO, STP, DFE, EBU),
117 MFP_XWAY(GPIO2, GPIO, STP, DFE, EPHY),
118 MFP_XWAY(GPIO3, GPIO, STP, EPHY, EBU),
[all …]
/linux/arch/arm/boot/dts/moxa/
H A Dmoxart.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* moxart.dtsi - Device Tree Include file for MOXA ART family SoC
7 #include <dt-bindings/interrupt-controller/irq.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
14 interrupt-parent = <&intc>;
17 #address-cells = <1>;
18 #size-cells = <0>;
28 #address-cells = <1>;
29 #size-cells = <0>;
[all …]
/linux/arch/arm/boot/dts/gemini/
H A Dgemini-dlink-dns-313.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree file for D-Link DNS-313 1-Bay Network Storage Enclosure
6 /dts-v1/;
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/thermal/thermal.h>
13 model = "D-Link DNS-313 1-Bay Network Storage Enclosure";
14 compatible = "dlink,dns-313", "cortina,gemini";
15 #address-cells = <1>;
16 #size-cells = <1>;
19 /* 64 MB SDRAM in a Nanya NT5DS32M16BS-6K package */
[all …]
H A Dgemini-sq201.dts1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
9 #include <dt-bindings/input/input.h>
14 #address-cells = <1>;
15 #size-cells = <1>;
24 stdout-path = &uart0;
28 compatible = "gpio-keys";
30 button-setup {
31 debounce-interval = <100>;
32 wakeup-source;
[all …]
/linux/arch/powerpc/boot/dts/fsl/
H A Dmpc8569mds.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
8 /include/ "mpc8569si-pre.dtsi"
13 #address-cells = <2>;
14 #size-cells = <2>;
15 interrupt-parent = <&mpic>;
40 #address-cells = <1>;
41 #size-cells = <1>;
42 compatible = "cfi-flash";
44 bank-width = <1>;
45 device-width = <1>;
[all …]
/linux/arch/powerpc/platforms/pasemi/
H A Dgpio_mdio.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2006-2007 PA Semi, Inc
9 * Based on drivers/net/fs_enet/mii-bitbang.c.
34 #define MDC_PIN(bus) (((struct gpio_priv *)bus->priv)->mdc_pin)
35 #define MDIO_PIN(bus) (((struct gpio_priv *)bus->priv)->mdio_pin)
124 /* tri-state our MDIO I/O pin so we can read */ in gpio_mdio_read()
190 * Tri-state the MDIO line. in gpio_mdio_write()
202 /*nothing here - dunno how to reset it*/ in gpio_mdio_reset()
209 struct device *dev = &ofdev->dev; in gpio_mdio_probe()
210 struct device_node *np = ofdev->dev.of_node; in gpio_mdio_probe()
[all …]

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