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Searched full:mch (Results 1 – 25 of 35) sorted by relevance

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/linux/drivers/pnp/
H A Dquirks.c331 /* Device IDs of parts that have 32KB MCH space */
358 struct resource mch; in quirk_intel_mch() local
367 * MCHBAR is not an architected PCI BAR, so MCH space is usually in quirk_intel_mch()
368 * reported as a PNP0C02 resource. The MCH space was originally in quirk_intel_mch()
371 * MCH space is consumed but unreported. in quirk_intel_mch()
385 memset(&mch, 0, sizeof(mch)); in quirk_intel_mch()
386 mch.flags = IORESOURCE_MEM; in quirk_intel_mch()
387 pcibios_bus_to_resource(host->bus, &mch, &region); in quirk_intel_mch()
391 if (res->end < mch.start || res->start > mch.end) in quirk_intel_mch()
393 if (res->start == mch.start && res->end == mch.end) in quirk_intel_mch()
[all …]
/linux/drivers/gpu/drm/i915/
H A Dintel_mchbar_regs.h31 /* Pineview MCH register contains DDR3 setting */
35 /* 915-945 and GM965 MCH register controlling DRAM channel access */
46 /* 965 MCH register controlling DRAM channel configuration */
139 /* snb MCH registers for reading the DRAM channel configuration */
225 /* snb MCH registers for priority tuning */
/linux/drivers/hwmon/
H A Dabituguru3.c192 { "MCH & PCIE 1.5V", 4, 0, 10, 1, 0 },
193 { "MCH 2.5V", 5, 0, 20, 1, 0 },
214 { "MCH & PCIE 1.5V", 4, 0, 10, 1, 0 },
215 { "MCH 2.5V", 5, 0, 20, 1, 0 },
243 { "MCH & PCIE 1.5V", 4, 0, 10, 1, 0 },
244 { "MCH 2.5V", 5, 0, 20, 1, 0 },
265 { "MCH & PCIE 1.5V", 4, 0, 10, 1, 0 },
266 { "MCH 2.5V", 5, 0, 20, 1, 0 },
357 { "MCH & PCIE 1.5V", 4, 0, 10, 1, 0 },
358 { "MCH 2.5V", 5, 0, 20, 1, 0 },
[all …]
/linux/drivers/edac/
H A DKconfig187 i5400 MCH chipset (Seaburg).
221 tristate "Intel San Clemente MCH"
225 San Clemente MCH.
228 tristate "Intel Clarksboro MCH"
232 Clarksboro MCH (Intel 7300 chipset).
H A Di3000_edac.c27 #define I3000_MCHBAR 0x44 /* MCH Memory Mapped Register BAR */
76 * 11 MCH Thermal Sensor Event
92 * 11 SERR on MCH Thermal Sensor Event
H A Dx38_edac.c31 #define X38_MCHBAR_LOW 0x48 /* MCH Memory Mapped Register BAR */
52 * 11 MCH Thermal Sensor Event
H A Di7300_edac.c10 * Intel 7300 Chipset Memory Controller Hub (MCH) - Datasheet
258 [31] = "Internal MCH Fatal Error",
274 [15] = "Internal MCH Non-Fatal Error",
924 * i7300_get_devices() - Find and perform 'get' operation on the MCH's
941 /* Attempt to 'get' the MCH register we want */ in i7300_get_devices()
H A Di3200_edac.c31 #define I3200_MCHBAR_LOW 0x48 /* MCH Memory Mapped Register BAR */
52 * 11 MCH Thermal Sensor Event
H A Di5000_edac.c12 * Intel 5000X Chipset Memory Controller Hub (MCH) - Datasheet
357 /* I5000 MCH error information retrieved from Hardware */
774 * i5000_get_devices Find and perform 'get' operation on the MCH's
787 /* Attempt to 'get' the MCH register we want */ in i5000_get_devices()
813 /* Attempt to 'get' the MCH register we want */ in i5000_get_devices()
H A Di5400_edac.c18 * Intel 5400 Chipset Memory Controller Hub (MCH) - Datasheet
357 /* I5400 MCH error information retrieved from Hardware */
713 * i5400_get_devices Find and perform 'get' operation on the MCH's
729 /* Attempt to 'get' the MCH register we want */ in i5400_get_devices()
H A Di82875p_edac.c68 * 5 MCH detects unimplemented cycle
H A Die31200_edac.c115 * 11 MCH Thermal Sensor Event
H A Di5100_edac.c9 * Intel 5100X Chipset Memory Controller Hub (MCH) - Datasheet
/linux/arch/microblaze/boot/dts/
H A Dsystem.dts125 compatible = "xlnx,xps-mch-emc-2.00.a", "cfi-flash";
136 xlnx,mch-native-dwidth = <0x20>;
137 xlnx,mch-plb-clk-period-ps = <0x1f40>;
138 xlnx,mch-splb-awidth = <0x20>;
/linux/drivers/net/wireless/broadcom/brcm80211/brcmsmac/
H A Dampdu.c617 u16 mch; in brcms_c_ampdu_finalize() local
742 mch = le16_to_cpu(txh->MacTxControlHigh); in brcms_c_ampdu_finalize()
747 if ((mch & TXC_PREAMBLE_RTS_MAIN_SHORT) == in brcms_c_ampdu_finalize()
751 if ((mch & TXC_PREAMBLE_RTS_FB_SHORT) == in brcms_c_ampdu_finalize()
775 mch |= TXC_AMPDU_FBR; in brcms_c_ampdu_finalize()
776 txh->MacTxControlHigh = cpu_to_le16(mch); in brcms_c_ampdu_finalize()
/linux/Documentation/devicetree/bindings/regulator/
H A Dmediatek,mt6331-regulator.yaml39 "^ldo-v(dig18|emc33|ibr|mc|mch|mipi|rtc|sram|usb10)$":
45 pattern: "^v(dig18|emc33|ibr|mc|mch|mipi|rtc|sram|usb10)$"
H A Dmediatek,mt6397-regulator.yaml53 "^(ldo_)?v(cama|emc3v3|gp[123456]|ibr|mc|mch)$":
H A Dmediatek,mt6358-regulator.yaml127 "^(ldo_)?v(cama[12]|camd|cn33|dram2|efuse|emc|ibr|ldo28|m18|mc|mch|mddr|sim[12])$":
H A Dmediatek,mt6357-regulator.yaml46 "^ldo-v(efuse|ibr|ldo28|mch|cama|camd|cn33-bt|cn33-wifi)$":
/linux/drivers/gpu/drm/i915/soc/
H A Dintel_gmch.c41 /* Allocate space for the MCH regs if needed, return nonzero on error */
/linux/Documentation/devicetree/bindings/mtd/
H A Dmtd-physmap.yaml50 - xlnx,xps-mch-emc-2.00.a
/linux/drivers/platform/x86/
H A Dintel_ips.c323 /* Optional MCH interfaces for if i915 is in use */
652 * Check the MCH temp & power against their maximums.
853 return 0; /* MCH temp reporting buggy */ in read_mgtv()
1070 /* MCH */ in ips_monitor()
/linux/arch/s390/kernel/
H A Dnmi.c180 * So we just stop listening for the WARNING MCH and avoid continuously in s390_handle_mcck()
/linux/drivers/gpu/drm/i915/gt/
H A Dintel_ggtt_fencing.c540 * is called "Channel XOR Randomization" in the MCH documentation. The result
/linux/Documentation/admin-guide/laptops/
H A Dthinkpad-acpi.rst941 - 9: MCH (northbridge) to DRAM Bus
953 - 5: MCH (northbridge)

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