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/freebsd/cddl/contrib/opensolaris/cmd/dtrace/test/tst/common/java_api/
H A Dtst.Bean.ksh.out45 …max = 10, frequency = 0], org.opensolaris.os.dtrace.Distribution$Bucket[min = 11, max = 20, freque…
56 …max = 10, frequency = 0], org.opensolaris.os.dtrace.Distribution$Bucket[min = 11, max = 20, freque…
68 …max = 10, frequency = 0], org.opensolaris.os.dtrace.Distribution$Bucket[min = 11, max = 20, freque…
79 …max = 10, frequency = 0], org.opensolaris.os.dtrace.Distribution$Bucket[min = 11, max = 20, freque…
150 …-4611686018427387904, max = -2305843009213693953, frequency = 0], org.opensolaris.os.dtrace.Distri…
151 …-4611686018427387904, max = -2305843009213693953, frequency = 0], org.opensolaris.os.dtrace.Distri…
153 …-4611686018427387904, max = -2305843009213693953, frequency = 0], org.opensolaris.os.dtrace.Distri…
154 …-4611686018427387904, max = -2305843009213693953, frequency = 0], org.opensolaris.os.dtrace.Distri…
156 …max = 10, frequency = 0], org.opensolaris.os.dtrace.Distribution$Bucket[min = 11, max = 20, freque…
157 …max = 10, frequency = 0], org.opensolaris.os.dtrace.Distribution$Bucket[min = 11, max = 20, freque…
[all …]
/freebsd/sys/contrib/device-tree/src/arm/qcom/
H A Dqcom-msm8960-cdp.dts1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/input/input.h>
4 #include "qcom-msm8960.dtsi"
9 compatible = "qcom,msm8960-cdp", "qcom,msm8960";
16 stdout-path = "serial0:115200n8";
19 ext_l2: gpio-regulator {
20 compatible = "regulator-fixed";
21 regulator-nam
[all...]
H A Dqcom-msm8960-samsung-expressatt.dts1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/input/input.h>
3 #include <dt-bindings/reset/qcom,gcc-msm8960.h>
5 #include "qcom-msm8960.dtsi"
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
9 #include <dt-bindings/input/gpio-keys.h>
12 model = "Samsung Galaxy Express SGH-I437";
14 chassis-type = "handset";
23 stdout-path = "serial0:115200n8";
[all …]
H A Dqcom-apq8064-sony-xperia-lagan-yuga.dts1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/gpio/gpio.h>
3 #include <dt-bindings/input/input.h>
4 #include <dt-bindings/mfd/qcom-rpm.h>
5 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
7 #include "qcom-apq8064-v2.0.dtsi"
13 compatible = "sony,xperia-yuga", "qcom,apq8064";
14 chassis-type = "handset";
21 stdout-path = "serial0:115200n8";
24 gpio-keys {
[all …]
H A Dqcom-ipq8064-v2.0-smb208.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include "qcom-ipq8064-v2.0.dtsi"
7 compatible = "qcom,rpm-smb208-regulators";
10 regulator-min-microvolt = <1050000>;
11 regulator-max-microvolt = <1150000>;
13 qcom,switch-mode-frequency = <1200000>;
17 regulator-min-microvolt = <1050000>;
18 regulator-max-microvolt = <1150000>;
20 qcom,switch-mode-frequency = <1200000>;
24 regulator-min-microvolt = < 800000>;
[all …]
H A Dqcom-ipq8062-smb208.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 #include "qcom-ipq8062.dtsi"
7 compatible = "qcom,rpm-smb208-regulators";
10 regulator-min-microvolt = <1050000>;
11 regulator-max-microvolt = <1150000>;
13 qcom,switch-mode-frequency = <1200000>;
17 regulator-min-microvolt = <1050000>;
18 regulator-max-microvolt = <1150000>;
20 qcom,switch-mode-frequency = <1200000>;
24 regulator-min-microvolt = < 800000>;
[all …]
H A Dqcom-ipq8065-smb208.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include "qcom-ipq8065.dtsi"
7 compatible = "qcom,rpm-smb208-regulators";
10 regulator-min-microvolt = <1050000>;
11 regulator-max-microvolt = <1150000>;
13 qcom,switch-mode-frequency = <1200000>;
17 regulator-min-microvolt = <1050000>;
18 regulator-max-microvolt = <1150000>;
20 qcom,switch-mode-frequency = <1200000>;
24 regulator-min-microvolt = <775000>;
[all …]
H A Dqcom-ipq8064-smb208.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include "qcom-ipq8064.dtsi"
7 compatible = "qcom,rpm-smb208-regulators";
10 regulator-min-microvolt = <1050000>;
11 regulator-max-microvolt = <1150000>;
13 qcom,switch-mode-frequency = <1200000>;
17 regulator-min-microvolt = <1050000>;
18 regulator-max-microvolt = <1150000>;
20 qcom,switch-mode-frequency = <1200000>;
24 regulator-min-microvolt = < 800000>;
[all …]
H A Dqcom-apq8064-cm-qs600.dts1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/gpio/gpio.h>
3 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
5 #include "qcom-apq8064-v2.0.dtsi"
10 model = "CompuLab CM-QS600";
11 compatible = "qcom,apq8064-cm-qs600", "qcom,apq8064";
18 stdout-path = "serial0:115200n8";
21 sdcc4_pwrseq: pwrseq-sdcc4 {
22 pinctrl-names = "default";
23 pinctrl-0 = <&wlan_default_gpios>;
[all …]
H A Dqcom-apq8064-asus-nexus7-flo.dts1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/gpio/gpio.h>
3 #include <dt-bindings/input/input.h>
4 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
6 #include "qcom-apq8064-v2.0.dtsi"
12 compatible = "asus,nexus7-flo", "qcom,apq8064";
13 chassis-type = "tablet";
21 stdout-path = "serial0:115200n8";
24 reserved-memory {
25 #address-cells = <1>;
[all …]
/freebsd/sys/dev/qat/qat_common/
H A Dadf_clock.c1 /* SPDX-License-Identifier: BSD-3-Clause */
2 /* Copyright(c) 2007-2022 Intel Corporation */
13 #define CLK_DBGFS_FILE "frequency"
27 struct adf_hw_device_data *hw_data = accel_dev->hw_device; in adf_clock_debugfs_add()
34 device_get_sysctl_ctx(accel_dev->accel_pci_dev.pci_dev); in adf_clock_debugfs_add()
36 device_get_sysctl_tree(accel_dev->accel_pci_dev.pci_dev); in adf_clock_debugfs_add()
43 &hw_data->clock_frequency, in adf_clock_debugfs_add()
45 "clock frequency"); in adf_clock_debugfs_add()
51 * adf_dev_measure_clock() -- Measure the CPM clock frequency
53 * @frequency: Pointer to returned frequency in Hz.
[all …]
/freebsd/sys/contrib/device-tree/Bindings/iio/resolver/
H A Dad2s90.txt1 Analog Devices AD2S90 Resolver-to-Digital Converter
6 - compatible: should be "adi,ad2s90"
7 - reg: SPI chip select number for the device
8 - spi-max-frequency: set maximum clock frequency, must be 830000
9 - spi-cpol and spi-cpha:
11 spi-cpha, spi-cpol.
14 Documentation/devicetree/bindings/spi/spi-bus.txt
16 Note about max frequency:
17 Chip's max frequency, as specified in its datasheet, is 2Mhz. But a 600ns
21 2 * 600ns, so the max frequency should be 1 / (2 * 6e-7), which gives
[all …]
/freebsd/sys/contrib/device-tree/src/arm/broadcom/
H A Dbcm28155-ap.dts1 // SPDX-License-Identifier: GPL-2.0-only
4 /dts-v1/;
6 #include <dt-bindings/gpio/gpio.h>
12 compatible = "brcm,bcm28155-ap", "brcm,bcm11351";
21 clock-frequency = <400000>;
26 clock-frequenc
[all...]
/freebsd/contrib/ntp/kernel/sys/
H A Dtimex.h21 * Added defines for hybrid phase/frequency-lock loop.
25 * defines for PPS phase-lock loop.
45 * ntp_gettime - NTP user application interface
56 * ntp_adjtime - NTP daemon application interface
76 * phase-lock loop (PLL) model used in the kernel implementation. These
81 * establishes the timer interrupt frequency, 100 Hz for the SunOS
98 #define SHIFT_KF 16 /* PLL frequency factor (shift) */
99 #define SHIFT_KH 2 /* FLL frequency factor (shift) */
105 * possible without overflow of a 32-bit word.
108 * which serves as a an extension to the low-order bits of the system
[all …]
/freebsd/sys/contrib/device-tree/src/arm/samsung/
H A Dexynos5422-cpus.dtsi1 // SPDX-License-Identifier: GPL-2.0
13 * Exynos5420 and Exynos5800 always boot from Cortex-A15. On Exynos5422
15 * the gpg2-1 GPIO. By default all Exynos5422 based boards choose booting
16 * from the LITTLE: Cortex-A7.
21 #address-cells = <1>;
22 #size-cells = <0>;
24 cpu-map {
58 compatible = "arm,cortex-a7";
61 clock-frequency = <1000000000>;
62 cci-control-port = <&cci_control0>;
[all …]
H A Dexynos5420-cpus.dtsi1 // SPDX-License-Identifier: GPL-2.0
14 * Exynos5420 and Exynos5800 always boot from Cortex-A15. On Exynos5422
16 * the gpg2-1 GPIO. By default all Exynos5422 based boards choose booting
17 * from the LITTLE: Cortex-A7.
22 #address-cells = <1>;
23 #size-cells = <0>;
25 cpu-map {
59 compatible = "arm,cortex-a15";
62 clock-frequency = <1800000000>;
63 cci-control-port = <&cci_control1>;
[all …]
/freebsd/sys/contrib/device-tree/src/riscv/sifive/
H A Dhifive-unmatched-a00.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
4 #include "fu740-c000.dtsi"
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/interrupt-controller/irq.h>
7 #include <dt-bindings/leds/common.h>
8 #include <dt-bindings/pwm/pwm.h>
10 /* Clock frequency (i
[all...]
H A Dhifive-unleashed-a00.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2018-2019 SiFive, Inc */
4 #include "fu540-c000.dtsi"
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/leds/common.h>
7 #include <dt-bindings/pwm/pwm.h>
9 /* Clock frequency (in Hz) of the PCB crystal for rtcclk */
14 compatible = "sifive,hifive-unleashed-a00", "sifive,fu540-c000",
18 stdout-path = "serial0";
22 timebase-frequency = <RTCCLK_FREQ>;
[all …]
/freebsd/sys/contrib/device-tree/Bindings/spi/
H A Dqcom,spi-qup.txt4 and an input FIFO) for serial peripheral interface (SPI) mini-core.
10 - compatible: Should contain:
11 "qcom,spi-qup-v1.1.1" for 8660, 8960 and 8064.
12 "qcom,spi-qup-v2.1.1" for 8974 and later
13 "qcom,spi-qup-v2.2.1" for 8974 v2 and later.
15 - reg: Should contain base register location and length
16 - interrupts: Interrupt number used by this controller
18 - clocks: Should contain the core clock and the AHB clock.
19 - clock-names: Should be "core" for the core clock and "iface" for the
22 - #address-cells: Number of cells required to define a chip select
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/freescale/
H A Dfsl-ls1028a-qds.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
11 /dts-v1/;
13 #include "fsl-ls1028a.dtsi"
17 compatible = "fsl,ls1028a-qds", "fsl,ls1028a";
32 stdout-path = "serial0:115200n8";
40 sys_mclk: clock-mclk {
41 compatible = "fixed-clock";
42 #clock-cells = <0>;
43 clock-frequency = <25000000>;
46 reg_1p8v: regulator-1p8v {
[all …]
H A Dfsl-ls1012a-qds.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 /dts-v1/;
10 #include "fsl-ls1012a.dtsi"
14 compatible = "fsl,ls1012a-qds", "fsl,ls1012a";
21 sys_mclk: clock-mclk {
22 compatible = "fixed-clock";
23 #clock-cells = <0>;
24 clock-frequency = <24576000>;
27 reg_3p3v: regulator-3p3v {
28 compatible = "regulator-fixed";
[all …]
/freebsd/sys/contrib/device-tree/src/arm/microchip/
H A Dat91-sama5d4_ma5d4.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
18 clock-frequency = <32768>;
22 clock-frequency = <12000000>;
26 compatible = "fixed-clock";
27 #clock-cells = <0>;
28 clock-frequency = <20000000>;
29 clock-output-names = "clk20m";
36 pinctrl-names = "default";
37 pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_dat4_7>;
38 vmmc-supply = <&vcc_mmc0_reg>;
[all …]
/freebsd/sys/contrib/device-tree/Bindings/net/wireless/
H A Dti,wlcore,spi.txt7 - compatible : Should be one of the following:
18 - reg : Chip select address of device
19 - spi-max-frequency : Maximum SPI clocking speed of device in Hz
20 - interrupts : Should contain parameters for 1 interrupt line.
21 - vwlan-supply : Point the node of the regulator that powers/enable the
25 - ref-clock-frequency : Reference clock frequency (should be set for wl12xx)
26 - clock-xtal : boolean, clock is generated from XTAL
28 - Please consult Documentation/devicetree/bindings/spi/spi-bus.txt
38 spi-max-frequency = <48000000>;
39 interrupt-parent = <&gpio3>;
[all …]
/freebsd/sys/contrib/device-tree/Bindings/mmc/
H A Dcavium-mmc.txt10 - compatible : should be one of:
11 cavium,octeon-6130-mmc
12 cavium,octeon-7890-mmc
13 cavium,thunder-8190-mmc
14 cavium,thunder-8390-mmc
15 mmc-slot
16 - reg : mmc controller base registers
17 - clocks : phandle
20 - for cd, bus-width and additional generic mmc parameters
22 - cavium,cmd-clk-skew : number of coprocessor clocks before sampling command
[all …]
/freebsd/sys/contrib/device-tree/src/riscv/starfive/
H A Djh7110-common.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 /dts-v1/;
9 #include "jh7110-pinfunc.h"
10 #include <dt-bindings/gpio/gpio.h>
25 stdout-path = "serial0:115200n8";
33 gpio-restart {
34 compatible = "gpio-restart";
39 pwmdac_codec: audio-codec {
40 compatible = "linux,spdif-dit";
41 #sound-dai-cells = <0>;
[all …]

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