Home
last modified time | relevance | path

Searched +full:max +full:- +full:frequency (Results 1 – 25 of 1027) sorted by relevance

12345678910>>...42

/linux/include/linux/clk/
H A Drenesas.h1 /* SPDX-License-Identifier: GPL-2.0+
13 #include <linux/clk-provider.h>
50 * struct rzv2h_pll_limits - PLL parameter constraints
56 * @input_fref: Reference input frequency to the PLL (in Hz). If set
59 * @fout: Output frequency range (in MHz)
60 * @fout.min: Minimum allowed output frequency
61 * @fout.max: Maximum allowed output frequency
63 * @fvco: PLL oscillation frequency range (in MHz)
64 * @fvco.min: Minimum allowed VCO frequency
65 * @fvco.max: Maximum allowed VCO frequency
[all …]
/linux/Documentation/netlink/specs/
H A Ddpll.yaml1 # SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause)
2 ---
8 -
16 -
20 -
23 render-max: true
24 -
26 name: lock-status
31 -
37 -
[all …]
/linux/arch/arm/boot/dts/qcom/
H A Dqcom-msm8960-cdp.dts1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/input/input.h>
4 #include "qcom-msm8960.dtsi"
9 compatible = "qcom,msm8960-cdp", "qcom,msm8960";
16 stdout-path = "serial0:115200n8";
19 ext_l2: gpio-regulator {
20 compatible = "regulator-fixed";
21 regulator-name = "ext_l2";
23 startup-delay-us = <10000>;
24 enable-active-high;
[all …]
H A Dqcom-msm8960-sony-huashan.dts1 // SPDX-License-Identifier: GPL-2.0-only
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/input/input.h>
7 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
8 #include <dt-bindings/reset/qcom,gcc-msm8960.h>
10 #include "qcom-msm8960.dtsi"
16 chassis-type = "handset";
25 stdout-path = "serial0:115200n8";
28 gpio-keys {
29 compatible = "gpio-keys";
[all …]
H A Dqcom-apq8064-sony-xperia-lagan-yuga.dts1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/gpio/gpio.h>
3 #include <dt-bindings/input/input.h>
4 #include <dt-bindings/mfd/qcom-rpm.h>
5 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
7 #include "qcom-apq8064-v2.0.dtsi"
13 compatible = "sony,xperia-yuga", "qcom,apq8064";
14 chassis-type = "handset";
21 stdout-path = "serial0:115200n8";
24 gpio-keys {
[all …]
H A Dqcom-apq8064-cm-qs600.dts1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/gpio/gpio.h>
3 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
5 #include "qcom-apq8064-v2.0.dtsi"
10 model = "CompuLab CM-QS600";
11 compatible = "qcom,apq8064-cm-qs600", "qcom,apq8064";
18 stdout-path = "serial0:115200n8";
21 sdcc4_pwrseq: pwrseq-sdcc4 {
22 pinctrl-names = "default";
23 pinctrl-0 = <&wlan_default_gpios>;
[all …]
H A Dqcom-apq8064-asus-nexus7-flo.dts1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/gpio/gpio.h>
3 #include <dt-bindings/input/input.h>
4 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
6 #include "qcom-apq8064-v2.0.dtsi"
12 compatible = "asus,nexus7-flo", "qcom,apq8064";
13 chassis-type = "tablet";
21 stdout-path = "serial0:115200n8";
24 reserved-memory {
25 #address-cells = <1>;
[all …]
/linux/arch/arm/boot/dts/broadcom/
H A Dbcm28155-ap.dts1 // SPDX-License-Identifier: GPL-2.0-only
4 /dts-v1/;
6 #include <dt-bindings/gpio/gpio.h>
12 compatible = "brcm,bcm28155-ap", "brcm,bcm11351";
21 clock-frequency = <400000>;
26 clock-frequency = <400000>;
31 clock-frequency = <400000>;
36 clock-frequency = <100000>;
46 regulator-min-microvolt = <3300000>;
47 regulator-max-microvolt = <3300000>;
[all …]
/linux/arch/arm/boot/dts/samsung/
H A Dexynos5422-cpus.dtsi1 // SPDX-License-Identifier: GPL-2.0
13 * Exynos5420 and Exynos5800 always boot from Cortex-A15. On Exynos5422
15 * the gpg2-1 GPIO. By default all Exynos5422 based boards choose booting
16 * from the LITTLE: Cortex-A7.
21 #address-cells = <1>;
22 #size-cells = <0>;
24 cpu-map {
58 compatible = "arm,cortex-a7";
61 clock-frequency = <1000000000>;
62 cci-control-port = <&cci_control0>;
[all …]
H A Dexynos5420-cpus.dtsi1 // SPDX-License-Identifier: GPL-2.0
14 * Exynos5420 and Exynos5800 always boot from Cortex-A15. On Exynos5422
16 * the gpg2-1 GPIO. By default all Exynos5422 based boards choose booting
17 * from the LITTLE: Cortex-A7.
22 #address-cells = <1>;
23 #size-cells = <0>;
25 cpu-map {
59 compatible = "arm,cortex-a15";
62 clock-frequency = <1800000000>;
63 cci-control-port = <&cci_control1>;
[all …]
/linux/arch/riscv/boot/dts/sifive/
H A Dhifive-unleashed-a00.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2018-2019 SiFive, Inc */
4 #include "fu540-c000.dtsi"
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/leds/common.h>
7 #include <dt-bindings/pwm/pwm.h>
9 /* Clock frequency (in Hz) of the PCB crystal for rtcclk */
14 compatible = "sifive,hifive-unleashed-a00", "sifive,fu540-c000",
18 stdout-path = "serial0";
22 timebase-frequency = <RTCCLK_FREQ>;
[all …]
H A Dhifive-unmatched-a00.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
4 #include "fu740-c000.dtsi"
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/interrupt-controller/irq.h>
7 #include <dt-bindings/leds/common.h>
8 #include <dt-bindings/pwm/pwm.h>
10 /* Clock frequency (in Hz) of the PCB crystal for rtcclk */
15 compatible = "sifive,hifive-unmatched-a00", "sifive,fu740-c000",
19 stdout-path = "serial0";
23 timebase-frequency = <RTCCLK_FREQ>;
[all …]
/linux/drivers/gpu/drm/i915/gt/
H A Dselftest_slpc.c1 // SPDX-License-Identifier: MIT
32 pr_err("Could not set min frequency to [%u]\n", freq); in slpc_set_min_freq()
45 pr_err("Could not set maximum frequency [%u]\n", in slpc_set_max_freq()
56 struct intel_guc_slpc *slpc = &gt_to_guc(gt)->slpc; in slpc_set_freq()
60 pr_err("Unable to update max freq"); in slpc_set_freq()
73 static int slpc_restore_freq(struct intel_guc_slpc *slpc, u32 min, u32 max) in slpc_restore_freq() argument
77 err = slpc_set_max_freq(slpc, max); in slpc_restore_freq()
79 pr_err("Unable to restore max freq"); in slpc_restore_freq()
120 *freq = intel_rps_read_actual_frequency(&gt->rps); in measure_power_at_freq()
121 *power = slpc_measure_power(&gt->rps, freq); in measure_power_at_freq()
[all …]
/linux/Documentation/scheduler/
H A Dsched-util-clamp.rst1 .. SPDX-License-Identifier: GPL-2.0
18 used, util clamp will influence the CPU frequency selection as well.
57 foreground, top-app, etc. Util clamp can be used to constrain how much
60 the ones belonging to the currently active app (top-app group). Beside this
65 1. The big cores are free to run top-app tasks immediately. top-app
89 higher frequency required for the tasks to finish their work in time. Setting
103 performance point rather than being tied to MAX frequency all the time. Which
106 Note that by design RT tasks don't have per-task PELT signal and must always
107 run at a constant frequency to combat undeterministic DVFS rampup delays.
109 Note that using schedutil always implies a single delay to modify the frequency
[all …]
/linux/drivers/clk/renesas/
H A Drzv2h-cpg-lib.c1 // SPDX-License-Identifier: GPL-2.0
17 * rzv2h_cpg_get_pll_pars - Finds the best combination of PLL parameters
18 * for a given frequency.
23 * @freq_millihz: Target output frequency in millihertz
26 * the desired frequency.
30 * (desired frequency - actual frequency).
37 unsigned long input_fref = limits->input_fref ?: (24 * MEGA); in rzv2h_cpg_get_pll_pars()
38 u64 fout_min_millihz = mul_u32_u32(limits->fout.min, MILLI); in rzv2h_cpg_get_pll_pars()
39 u64 fout_max_millihz = mul_u32_u32(limits->fout.max, MILLI); in rzv2h_cpg_get_pll_pars()
49 for (p.p = limits->p.min; p.p <= limits->p.max; p.p++) { in rzv2h_cpg_get_pll_pars()
[all …]
/linux/drivers/crypto/intel/qat/qat_common/
H A Dadf_clock.c1 // SPDX-License-Identifier: GPL-2.0-only
41 static int measure_clock(struct adf_accel_dev *accel_dev, u32 *frequency) in measure_clock() argument
58 delta_us = timespec_to_us(&ts2) - timespec_to_us(&ts1); in measure_clock()
59 } while (delta_us > MEASURE_CLOCK_DELTA_THRESHOLD_US && --tries); in measure_clock()
63 return -ETIMEDOUT; in measure_clock()
74 return -EIO; in measure_clock()
77 delta_us = timespec_to_us(&ts4) - timespec_to_us(&ts3); in measure_clock()
78 } while (delta_us > MEASURE_CLOCK_DELTA_THRESHOLD_US && --tries); in measure_clock()
82 return -ETIMEDOUT; in measure_clock()
85 delta_us = timespec_to_us(&ts3) - timespec_to_us(&ts1); in measure_clock()
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dfsl-ls1028a-qds.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
11 /dts-v1/;
13 #include "fsl-ls1028a.dtsi"
17 compatible = "fsl,ls1028a-qds", "fsl,ls1028a";
32 stdout-path = "serial0:115200n8";
40 sys_mclk: clock-mclk {
41 compatible = "fixed-clock";
42 #clock-cells = <0>;
43 clock-frequency = <25000000>;
46 reg_1p8v: regulator-1p8v {
[all …]
/linux/drivers/cpufreq/
H A Dcpufreq.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * (C) 2002 - 2003 Dominik Brodowski <linux@brodo.de>
9 * Oct 2005 - Ashok Raj <ashok.raj@intel.com>
11 * Feb 2006 - Jacob Shin <jacob.shin@amd.com>
12 * Fix handling for CPU hotplug -- affected CPUs
55 * The "cpufreq driver" - the arch- or hardware-dependent low
74 return cpufreq_driver->target_index || cpufreq_driver->target; in has_target()
79 return !!cpufreq_driver->target_index; in has_target_index()
95 * validation process for a new CPU frequency policy; the
118 return !!(cpufreq_driver->flags & CPUFREQ_HAVE_GOVERNOR_PER_POLICY); in have_governor_per_policy()
[all …]
/linux/tools/power/cpupower/utils/
H A Dcpufreq-info.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * (C) 2004-2009 Dominik Brodowski <linux@dominikbrodowski.de>
39 value[LINE_LEN - 1] = '\0'; in count_cpus()
40 if (strlen(value) < (LINE_LEN - 2)) in count_cpus()
62 unsigned long min, max; in proc_cpufreq_output() local
64 printf(_(" minimum CPU frequency - maximu in proc_cpufreq_output()
294 unsigned long min, max; get_hardware_limits() local
[all...]
/linux/arch/arm/boot/dts/microchip/
H A Dat91-sama5d4_ma5d4.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
18 clock-frequency = <32768>;
22 clock-frequency = <12000000>;
26 compatible = "fixed-clock";
27 #clock-cells = <0>;
28 clock-frequency = <20000000>;
29 clock-output-names = "clk20m";
36 pinctrl-names = "default";
37 pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_dat4_7>;
38 vmmc-supply = <&vcc_mmc0_reg>;
[all …]
/linux/Documentation/devicetree/bindings/mmc/
H A Dcavium-mmc.txt10 - compatible : should be one of:
11 cavium,octeon-6130-mmc
12 cavium,octeon-7890-mmc
13 cavium,thunder-8190-mmc
14 cavium,thunder-8390-mmc
15 mmc-slot
16 - reg : mmc controller base registers
17 - clocks : phandle
20 - for cd, bus-width and additional generic mmc parameters
22 - cavium,cmd-clk-skew : number of coprocessor clocks before sampling command
[all …]
/linux/drivers/memory/samsung/
H A Dexynos5422-dmc.c1 // SPDX-License-Identifier: GPL-2.0
10 #include <linux/devfreq-event.h>
101 * struct dmc_opp_table - Operating level desciption
102 * @freq_hz: target frequency in Hz
105 * Covers frequency and voltage settings of the DMC operating mode.
113 * struct exynos5_dmc - main structure describing DMC device
120 * @lock: protects curr_rate and frequency/voltage setting section
121 * @curr_rate: current frequency
160 /* Protects curr_rate and frequency/voltage setting section */
196 __val = (t_val) << (timing)->bit_beg; \
[all …]
/linux/kernel/sched/
H A Dcpufreq_schedutil.c1 // SPDX-License-Identifier: GPL-2.0
3 * CPUFreq governor based on scheduler-provided CPU utilization data.
55 /* The field below is for single-CPU policies only: */
68 * Cast rate_limit_us before multiplication to force 64-bit arithmetic. in sugov_update_rate_limit_us()
69 * Otherwise, on 32-bit platforms, both operands are converted to in sugov_update_rate_limit_us()
70 * 32-bit unsigned long and the multiplication may overflow. in sugov_update_rate_limit_us()
72 sg_policy->freq_update_delay_ns = in sugov_update_rate_limit_us()
73 (s64)sg_policy->tunables->rate_limit_us * NSEC_PER_USEC; in sugov_update_rate_limit_us()
81 * Since cpufreq_update_util() is called with rq->lock held for in sugov_should_update_freq()
82 * the @target_cpu, our per-CPU data is fully serialized. in sugov_should_update_freq()
[all …]
/linux/Documentation/devicetree/bindings/iio/resolver/
H A Dadi,ad2s90.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Analog Devices AD2S90 Resolver-to-Digital Converter
10 - Matheus Tavares <matheus.bernardino@usp.br>
22 spi-max-frequency:
25 Chip's max frequency, as specified in its datasheet, is 2Mhz. But a 600ns
29 most 2 * 600ns, so the max frequency should be 1 / (2 * 6e-7), which gives
32 spi-cpol: true
34 spi-cpha: true
[all …]
/linux/arch/riscv/boot/dts/starfive/
H A Djh7110-common.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 /dts-v1/;
9 #include "jh7110-pinfunc.h"
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/leds/common.h>
12 #include <dt-bindings/pinctrl/starfive,jh7110-pinctrl.h>
27 stdout-path = "serial0:115200n8";
33 bootph-pre-ram;
36 gpio-restart {
37 compatible = "gpio-restart";
[all …]

12345678910>>...42