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/linux/include/linux/clk/
H A Drenesas.h1 /* SPDX-License-Identifier: GPL-2.0+
13 #include <linux/clk-provider.h>
39 * struct rzv2h_pll_limits - PLL parameter constraints
45 * @fout: Output frequency range (in MHz)
46 * @fout.min: Minimum allowed output frequency
47 * @fout.max: Maximum allowed output frequency
49 * @fvco: PLL oscillation frequency range (in MHz)
50 * @fvco.min: Minimum allowed VCO frequency
51 * @fvco.max: Maximum allowed VCO frequency
53 * @m: Main-divider range
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/linux/Documentation/admin-guide/pm/
H A Dintel-speed-select.rst1 .. SPDX-License-Identifier: GPL-2.0
14 - https://www.intel.com/content/www/us/en/architecture-and-technology/speed-select-technology-artic…
15 - https://builders.intel.com/docs/networkbuilders/intel-speed-select-technology-base-frequency-enha…
19 dynamically without pre-configuring via BIOS setup options. This dynamic
29 intel-speed-select configuration tool
32 Most Linux distribution packages may include the "intel-speed-select" tool. If not,
38 # cd tools/power/x86/intel-speed-select/
43 ------------
47 # intel-speed-select --help
49 The top-level help describes arguments and features. Notice that there is a
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/linux/Documentation/cpu-freq/
H A Dcpu-drivers.rst1 .. SPDX-License-Identifier: GPL-2.0
10 - Dominik Brodowski <linux@brodo.de>
11 - Rafael J. Wysocki <rafael.j.wysocki@intel.com>
12 - Viresh Kumar <viresh.kumar@linaro.org>
18 1.2 Per-CPU Initialization
24 2. Frequency Table Helpers
31 So, you just got a brand-new CPU / chipset with datasheets and want to
37 ------------------
46 .name - The name of this driver.
48 .init - A pointer to the per-policy initialization function.
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/linux/Documentation/netlink/specs/
H A Ddpll.yaml1 # SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause)
2 ---
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/linux/include/linux/
H A Dcpufreq.h1 /* SPDX-License-Identifier: GPL-2.0-only */
6 * (C) 2002 - 2003 Dominik Brodowski <linux@brodo.de>
28 * Frequency values here are CPU kHz
49 /* in 10^(-9) s = nanoseconds */
67 unsigned int max; /* in kHz */ member
94 * - Any routine that wants to read from the policy structure will
96 * - An
188 unsigned int max; /* in kHz */ global() member
490 cpufreq_verify_within_limits(struct cpufreq_policy_data * policy,unsigned int min,unsigned int max) cpufreq_verify_within_limits() argument
712 unsigned int frequency; /* kHz - doesn't need to be in ascending global() member
854 find_index_l(struct cpufreq_policy * policy,unsigned int target_freq,unsigned int min,unsigned int max,bool efficiencies) find_index_l() argument
930 find_index_h(struct cpufreq_policy * policy,unsigned int target_freq,unsigned int min,unsigned int max,bool efficiencies) find_index_h() argument
1023 find_index_c(struct cpufreq_policy * policy,unsigned int target_freq,unsigned int min,unsigned int max,bool efficiencies) find_index_c() argument
1045 cpufreq_is_in_limits(struct cpufreq_policy * policy,unsigned int min,unsigned int max,int idx) cpufreq_is_in_limits() argument
1061 cpufreq_frequency_table_target(struct cpufreq_policy * policy,unsigned int target_freq,unsigned int min,unsigned int max,unsigned int relation) cpufreq_frequency_table_target() argument
1125 cpufreq_table_set_inefficient(struct cpufreq_policy * policy,unsigned int frequency) cpufreq_table_set_inefficient() argument
1203 cpufreq_table_set_inefficient(struct cpufreq_policy * policy,unsigned int frequency) cpufreq_table_set_inefficient() argument
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/linux/arch/arm/boot/dts/qcom/
H A Dqcom-msm8960-cdp.dts1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/input/input.h>
4 #include "qcom-msm8960.dtsi"
9 compatible = "qcom,msm8960-cdp", "qcom,msm8960";
16 stdout-path = "serial0:115200n8";
19 ext_l2: gpio-regulator {
20 compatible = "regulator-fixed";
21 regulator-name = "ext_l2";
23 startup-delay-us = <10000>;
24 enable-active-high;
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H A Dqcom-msm8960-sony-huashan.dts1 // SPDX-License-Identifier: GPL-2.0-only
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/input/input.h>
7 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
8 #include <dt-bindings/reset/qcom,gcc-msm8960.h>
10 #include "qcom-msm8960.dtsi"
16 chassis-type = "handset";
25 stdout-path = "serial0:115200n8";
28 gpio-keys {
29 compatible = "gpio-keys";
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H A Dqcom-mdm9615-wp8548.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
9 #include "qcom-mdm9615.dtsi"
23 pinctrl-0 = <&reset_out_pins>;
24 pinctrl-names = "default";
26 gsbi3_pins: gsbi3-state {
27 gsbi3-pins {
30 drive-strength = <8>;
31 bias-disable;
35 gsbi4_pins: gsbi4-state {
36 gsbi4-pins {
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H A Dqcom-apq8064-sony-xperia-lagan-yuga.dts1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/gpio/gpio.h>
3 #include <dt-bindings/input/input.h>
4 #include <dt-bindings/mfd/qcom-rpm.h>
5 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
7 #include "qcom-apq8064-v2.0.dtsi"
13 compatible = "sony,xperia-yuga", "qcom,apq8064";
14 chassis-type = "handset";
21 stdout-path = "serial0:115200n8";
24 gpio-keys {
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H A Dqcom-ipq8064-v2.0-smb208.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include "qcom-ipq8064-v2.0.dtsi"
7 compatible = "qcom,rpm-smb208-regulators";
10 regulator-min-microvolt = <1050000>;
11 regulator-max-microvolt = <1150000>;
13 qcom,switch-mode-frequency = <1200000>;
17 regulator-min-microvolt = <1050000>;
18 regulator-max-microvolt = <1150000>;
20 qcom,switch-mode-frequency = <1200000>;
24 regulator-min-microvolt = < 800000>;
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H A Dqcom-ipq8062-smb208.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 #include "qcom-ipq8062.dtsi"
7 compatible = "qcom,rpm-smb208-regulators";
10 regulator-min-microvolt = <1050000>;
11 regulator-max-microvolt = <1150000>;
13 qcom,switch-mode-frequency = <1200000>;
17 regulator-min-microvolt = <1050000>;
18 regulator-max-microvolt = <1150000>;
20 qcom,switch-mode-frequency = <1200000>;
24 regulator-min-microvolt = < 800000>;
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H A Dqcom-ipq8065-smb208.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include "qcom-ipq8065.dtsi"
7 compatible = "qcom,rpm-smb208-regulators";
10 regulator-min-microvolt = <1050000>;
11 regulator-max-microvolt = <1150000>;
13 qcom,switch-mode-frequency = <1200000>;
17 regulator-min-microvolt = <1050000>;
18 regulator-max-microvolt = <1150000>;
20 qcom,switch-mode-frequency = <1200000>;
24 regulator-min-microvolt = <775000>;
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H A Dqcom-ipq8064-smb208.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include "qcom-ipq8064.dtsi"
7 compatible = "qcom,rpm-smb208-regulators";
10 regulator-min-microvolt = <1050000>;
11 regulator-max-microvolt = <1150000>;
13 qcom,switch-mode-frequency = <1200000>;
17 regulator-min-microvolt = <1050000>;
18 regulator-max-microvolt = <1150000>;
20 qcom,switch-mode-frequency = <1200000>;
24 regulator-min-microvolt = < 800000>;
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H A Dqcom-msm8960-samsung-expressatt.dts1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/input/input.h>
3 #include <dt-bindings/reset/qcom,gcc-msm8960.h>
5 #include "qcom-msm8960.dtsi"
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/pinctrl/qcom,pmic-gpi
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/linux/arch/arm/boot/dts/broadcom/
H A Dbcm28155-ap.dts1 // SPDX-License-Identifier: GPL-2.0-only
4 /dts-v1/;
6 #include <dt-bindings/gpio/gpio.h>
12 compatible = "brcm,bcm28155-ap", "brcm,bcm11351";
21 clock-frequency = <400000>;
26 clock-frequency = <400000>;
31 clock-frequency = <400000>;
36 clock-frequency = <100000>;
46 regulator-min-microvolt = <3300000>;
47 regulator-max-microvolt = <3300000>;
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/linux/arch/arm/boot/dts/samsung/
H A Dexynos5422-cpus.dtsi1 // SPDX-License-Identifier: GPL-2.0
13 * Exynos5420 and Exynos5800 always boot from Cortex-A15. On Exynos5422
15 * the gpg2-1 GPIO. By default all Exynos5422 based boards choose booting
16 * from the LITTLE: Cortex-A7.
21 #address-cells = <1>;
22 #size-cells = <0>;
24 cpu-map {
58 compatible = "arm,cortex-a7";
61 clock-frequency = <1000000000>;
62 cci-control-port = <&cci_control0>;
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H A Dexynos5420-cpus.dtsi1 // SPDX-License-Identifier: GPL-2.0
14 * Exynos5420 and Exynos5800 always boot from Cortex-A15. On Exynos5422
16 * the gpg2-1 GPIO. By default all Exynos5422 based boards choose booting
17 * from the LITTLE: Cortex-A7.
22 #address-cells = <1>;
23 #size-cells = <0>;
25 cpu-map {
59 compatible = "arm,cortex-a15";
62 clock-frequency = <1800000000>;
63 cci-control-port = <&cci_control1>;
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/linux/arch/riscv/boot/dts/sifive/
H A Dhifive-unleashed-a00.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2018-2019 SiFive, Inc */
4 #include "fu540-c000.dtsi"
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/leds/common.h>
7 #include <dt-bindings/pwm/pwm.h>
9 /* Clock frequency (in Hz) of the PCB crystal for rtcclk */
14 compatible = "sifive,hifive-unleashed-a00", "sifive,fu540-c000",
18 stdout-path = "serial0";
22 timebase-frequency = <RTCCLK_FREQ>;
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H A Dhifive-unmatched-a00.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
4 #include "fu740-c000.dtsi"
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/interrupt-controller/irq.h>
7 #include <dt-bindings/leds/common.h>
8 #include <dt-bindings/pwm/pwm.h>
10 /* Clock frequency (in Hz) of the PCB crystal for rtcclk */
15 compatible = "sifive,hifive-unmatched-a00", "sifive,fu740-c000",
19 stdout-path = "serial0";
23 timebase-frequency = <RTCCLK_FREQ>;
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/linux/drivers/crypto/intel/qat/qat_common/
H A Dadf_clock.c1 // SPDX-License-Identifier: GPL-2.0-only
41 static int measure_clock(struct adf_accel_dev *accel_dev, u32 *frequency) in measure_clock() argument
58 delta_us = timespec_to_us(&ts2) - timespec_to_us(&ts1); in measure_clock()
59 } while (delta_us > MEASURE_CLOCK_DELTA_THRESHOLD_US && --tries); in measure_clock()
63 return -ETIMEDOUT; in measure_clock()
74 return -EIO; in measure_clock()
77 delta_us = timespec_to_us(&ts4) - timespec_to_us(&ts3); in measure_clock()
78 } while (delta_us > MEASURE_CLOCK_DELTA_THRESHOLD_US && --tries); in measure_clock()
82 return -ETIMEDOUT; in measure_clock()
85 delta_us = timespec_to_us(&ts3) - timespec_to_us(&ts1); in measure_clock()
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/linux/Documentation/scheduler/
H A Dsched-util-clamp.rst1 .. SPDX-License-Identifier: GPL-2.0
18 used, util clamp will influence the CPU frequency selection as well.
57 foreground, top-app, etc. Util clamp can be used to constrain how much
60 the ones belonging to the currently active app (top-app group). Beside this
65 1. The big cores are free to run top-app tasks immediately. top-app
89 higher frequency required for the tasks to finish their work in time. Setting
103 performance point rather than being tied to MAX frequency all the time. Which
106 Note that by design RT tasks don't have per-task PELT signal and must always
107 run at a constant frequency to combat undeterministic DVFS rampup delays.
109 Note that using schedutil always implies a single delay to modify the frequency
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/linux/arch/arm64/boot/dts/freescale/
H A Dfsl-ls1028a-qds.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
11 /dts-v1/;
13 #include "fsl-ls1028a.dtsi"
17 compatible = "fsl,ls1028a-qds", "fsl,ls1028a";
32 stdout-path = "serial0:115200n8";
40 sys_mclk: clock-mclk {
41 compatible = "fixed-clock";
42 #clock-cells = <0>;
43 clock-frequency = <25000000>;
46 reg_1p8v: regulator-1p8v {
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/linux/Documentation/devicetree/bindings/ufs/
H A Dufs-common.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/ufs/ufs-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alim Akhtar <alim.akhtar@samsung.com>
11 - Avri Altman <avri.altman@wdc.com>
16 clock-names: true
18 freq-table-hz:
21 - description: Minimum frequency for given clock in Hz
22 - description: Maximum frequency for given clock in Hz
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/linux/arch/arm/boot/dts/microchip/
H A Dat91-sama5d4_ma5d4.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
18 clock-frequency = <32768>;
22 clock-frequency = <12000000>;
26 compatible = "fixed-clock";
27 #clock-cells = <0>;
28 clock-frequency = <20000000>;
29 clock-output-names = "clk20m";
36 pinctrl-names = "default";
37 pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_dat4_7>;
38 vmmc-supply = <&vcc_mmc0_reg>;
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/linux/Documentation/devicetree/bindings/mmc/
H A Dcavium-mmc.txt10 - compatible : should be one of:
11 cavium,octeon-6130-mmc
12 cavium,octeon-7890-mmc
13 cavium,thunder-8190-mmc
14 cavium,thunder-8390-mmc
15 mmc-slot
16 - reg : mmc controller base registers
17 - clocks : phandle
20 - for cd, bus-width and additional generic mmc parameters
22 - cavium,cmd-clk-skew : number of coprocessor clocks before sampling command
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