Home
last modified time | relevance | path

Searched +full:mac +full:- +full:phy +full:- +full:ctrl (Results 1 – 25 of 142) sorted by relevance

123456

/linux/drivers/net/ethernet/intel/e1000e/
H A Dmac.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
9 * e1000e_get_bus_info_pcie - Get PCIe bus information
18 struct pci_dev *pdev = hw->adapter->pdev; in e1000e_get_bus_info_pcie()
19 struct e1000_mac_info *mac = &hw->mac; in e1000e_get_bus_info_pcie() local
20 struct e1000_bus_info *bus = &hw->bus; in e1000e_get_bus_info_pcie()
24 bus->width = e1000_bus_width_unknown; in e1000e_get_bus_info_pcie()
27 bus->width = (enum e1000_bus_width)FIELD_GET(PCI_EXP_LNKSTA_NLW, in e1000e_get_bus_info_pcie()
31 mac->ops.set_lan_id(hw); in e1000e_get_bus_info_pcie()
37 * e1000_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
[all …]
H A D82571.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
42 * e1000_init_phy_params_82571 - Init PHY func ptrs.
47 struct e1000_phy_info *phy = &hw->phy; in e1000_init_phy_params_82571() local
50 if (hw->phy.media_type != e1000_media_type_copper) { in e1000_init_phy_params_82571()
51 phy->type = e1000_phy_none; in e1000_init_phy_params_82571()
55 phy->addr = 1; in e1000_init_phy_params_82571()
56 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; in e1000_init_phy_params_82571()
57 phy->reset_delay_us = 100; in e1000_init_phy_params_82571()
59 phy->ops.power_up = e1000_power_up_phy_copper; in e1000_init_phy_params_82571()
[all …]
H A Dethtool.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
28 "s0ix-enabled",
30 "disable-k1",
38 .sizeof_stat = sizeof(((struct e1000_adapter *)0)->m), \
43 .sizeof_stat = sizeof(((struct rtnl_link_stats64 *)0)->m), \
117 struct e1000_hw *hw = &adapter->hw; in e1000_get_link_ksettings()
119 if (hw->phy.media_type == e1000_media_type_copper) { in e1000_get_link_ksettings()
129 if (hw->phy.type == e1000_phy_ife) in e1000_get_link_ksettings()
133 if (hw->mac.autoneg == 1) { in e1000_get_link_ksettings()
[all …]
H A D80003es2lan.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
35 * e1000_init_phy_params_80003es2lan - Init ESB2 PHY func ptrs.
40 struct e1000_phy_info *phy = &hw->phy; in e1000_init_phy_params_80003es2lan() local
43 if (hw->phy.media_type != e1000_media_type_copper) { in e1000_init_phy_params_80003es2lan()
44 phy->type = e1000_phy_none; in e1000_init_phy_params_80003es2lan()
47 phy->ops.power_up = e1000_power_up_phy_copper; in e1000_init_phy_params_80003es2lan()
48 phy->ops.power_down = e1000_power_down_phy_copper_80003es2lan; in e1000_init_phy_params_80003es2lan()
51 phy->addr = 1; in e1000_init_phy_params_80003es2lan()
52 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; in e1000_init_phy_params_80003es2lan()
[all …]
H A Dich8lan.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
5 * 82562G-2 10/100 Network Connection
7 * 82562GT-2 10/100 Network Connection
9 * 82562V-2 10/100 Network Connection
10 * 82566DC-2 Gigabit Network Connection
12 * 82566DM-2 Gigabit Network Connection
19 * 82567LM-2 Gigabit Network Connection
20 * 82567LF-2 Gigabit Network Connection
21 * 82567V-2 Gigabit Network Connection
[all …]
H A Dphy.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
37 * e1000e_check_reset_block_generic - Check if PHY reset is blocked
40 * Read the PHY management control register and check whether a PHY reset
54 * e1000e_get_phy_id - Retrieve the PHY ID and revision
57 * Reads the PHY registers and stores the PHY ID and possibly the PHY
62 struct e1000_phy_info *phy = &hw->phy; in e1000e_get_phy_id() local
67 if (!phy->ops.read_reg) in e1000e_get_phy_id()
75 phy->id = (u32)(phy_id << 16); in e1000e_get_phy_id()
81 phy->id |= (u32)(phy_id & PHY_REVISION_MASK); in e1000e_get_phy_id()
[all …]
H A Dnetdev.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
36 static int debug = -1;
68 {E1000_CTRL, "CTRL"},
113 * __ew32_prepare - prepare to write to MAC CSR register on certain parts
116 * When updating the MAC CSR registers, the Manageability Engine (ME) could
121 * has bit 24 set while ME is accessing MAC CSR registers, wait if it is set
128 while ((er32(FWSM) & E1000_ICH_FWSM_PCIM2PCI) && --i) in __ew32_prepare()
134 if (hw->adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) in __ew32()
137 writel(val, hw->hw_addr + reg); in __ew32()
[all …]
/linux/drivers/net/ethernet/intel/igc/
H A Digc_base.c1 // SPDX-License-Identifier: GPL-2.0
13 * igc_reset_hw_base - Reset hardware
22 u32 ctrl; in igc_reset_hw_base() local
24 /* Prevent the PCI-E bus from sticking if there is no TLP connection in igc_reset_hw_base()
25 * on the last TLP read/write transaction when MAC is reset. in igc_reset_hw_base()
29 hw_dbg("PCI-E Master disable polling has failed\n"); in igc_reset_hw_base()
40 ctrl = rd32(IGC_CTRL); in igc_reset_hw_base()
42 hw_dbg("Issuing a global reset to MAC\n"); in igc_reset_hw_base()
43 wr32(IGC_CTRL, ctrl | IGC_CTRL_RST); in igc_reset_hw_base()
62 * igc_init_nvm_params_base - Init NVM func ptrs.
[all …]
H A Digc_mac.c1 // SPDX-License-Identifier: GPL-2.0
11 * igc_disable_pcie_master - Disables PCI-express master access
14 * Returns 0 (0) if successful, else returns -10
15 * (-IGC_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused
18 * Disables PCI-Express master access and verifies there are no pending
25 u32 ctrl; in igc_disable_pcie_master() local
27 ctrl = rd32(IGC_CTRL); in igc_disable_pcie_master()
28 ctrl |= IGC_CTRL_GIO_MASTER_DISABLE; in igc_disable_pcie_master()
29 wr32(IGC_CTRL, ctrl); in igc_disable_pcie_master()
36 timeout--; in igc_disable_pcie_master()
[all …]
/linux/drivers/net/ethernet/intel/igb/
H A De1000_mac.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2007 - 2018 Intel Corporation. */
19 * igb_get_bus_info_pcie - Get PCIe bus information
28 struct e1000_bus_info *bus = &hw->bus; in igb_get_bus_info_pcie()
33 bus->type = e1000_bus_type_pci_express; in igb_get_bus_info_pcie()
39 bus->width = e1000_bus_width_unknown; in igb_get_bus_info_pcie()
40 bus->speed = e1000_bus_speed_unknown; in igb_get_bus_info_pcie()
44 bus->speed = e1000_bus_speed_2500; in igb_get_bus_info_pcie()
47 bus->speed = e1000_bus_speed_5000; in igb_get_bus_info_pcie()
50 bus->speed = e1000_bus_speed_unknown; in igb_get_bus_info_pcie()
[all …]
H A De1000_phy.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2007 - 2018 Intel Corporation. */
31 * igb_check_reset_block - Check if PHY reset is blocked
34 * Read the PHY management control register and check whether a PHY reset
48 * igb_get_phy_id - Retrieve the PHY ID and revision
51 * Reads the PHY registers and stores the PHY ID and possibly the PHY
56 struct e1000_phy_info *phy = &hw->phy; in igb_get_phy_id() local
60 /* ensure PHY page selection to fix misconfigured i210 */ in igb_get_phy_id()
61 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211)) in igb_get_phy_id()
62 phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0); in igb_get_phy_id()
[all …]
/linux/drivers/net/ethernet/samsung/sxgbe/
H A Dsxgbe_core.c1 // SPDX-License-Identifier: GPL-2.0-only
15 #include <linux/phy.h>
20 /* MAC core initialization */
43 /* Dump MAC registers */
87 /* Set/Get Unicast MAC addresses */
188 u32 ctrl; in sxgbe_set_eee_mode() local
191 * When Tx Automate bit is set, MAC internally handles the entry in sxgbe_set_eee_mode()
195 ctrl = readl(ioaddr + SXGBE_CORE_LPI_CTRL_STATUS); in sxgbe_set_eee_mode()
196 ctrl |= LPI_CTRL_STATUS_LPIEN | LPI_CTRL_STATUS_TXA; in sxgbe_set_eee_mode()
197 writel(ctrl, ioaddr + SXGBE_CORE_LPI_CTRL_STATUS); in sxgbe_set_eee_mode()
[all …]
/linux/drivers/net/dsa/microchip/
H A Dksz8.c1 // SPDX-License-Identifier: GPL-2.0
6 * - KSZ8463
7 * - KSZ8863, KSZ8873 aka KSZ88X3
8 * - KSZ8895, KSZ8864 aka KSZ8895 family
9 * - KSZ8794, KSZ8795, KSZ8765 aka KSZ87XX
11 * - KSZ8563, KSZ8567 - see KSZ9477 driver
24 #include <linux/platform_data/microchip-ksz.h>
25 #include <linux/phy.h>
45 ksz_rmw8(dev, dev->dev_ops->get_port_addr(port, offset), bits, in ksz_port_cfg()
50 * ksz8_ind_write8 - EEE/ACL/PME indirect register write
[all …]
/linux/drivers/net/ethernet/intel/ixgbe/
H A Dixgbe_82598.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
26 * ixgbe_set_pcie_completion_timeout - set pci-e completion timeout
31 * than the 10ms recommended by the pci-e spec. To address this we need to
40 if (ixgbe_removed(hw->hw_addr)) in ixgbe_set_pcie_completion_timeout()
72 struct ixgbe_mac_info *mac = &hw->mac; in ixgbe_get_invariants_82598() local
74 /* Call PHY identify routine to get the phy type */ in ixgbe_get_invariants_82598()
77 mac->mcft_size = IXGBE_82598_MC_TBL_SIZE; in ixgbe_get_invariants_82598()
78 mac->vft_size = IXGBE_82598_VFT_TBL_SIZE; in ixgbe_get_invariants_82598()
79 mac->num_rar_entries = IXGBE_82598_RAR_ENTRIES; in ixgbe_get_invariants_82598()
[all …]
/linux/drivers/net/ethernet/marvell/
H A Dskge.h1 /* SPDX-License-Identifier: GPL-2.0 */
133 CS_CLK_RUN_HOT = 1<<13,/* CLK_RUN hot m. (YUKON-Lite only) */
134 CS_CLK_RUN_RST = 1<<12,/* CLK_RUN reset (YUKON-Lite only) */
135 CS_CLK_RUN_ENA = 1<<11,/* CLK_RUN enable (YUKON-Lite only) */
175 IS_EXT_REG = 1<<23, /* IRQ from LM80 or PHY (GENESIS only) */
176 /* IRQ from PHY (YUKON only) */
178 IS_MAC1 = 1<<21, /* IRQ from MAC 1 */
179 IS_LNK_SYNC_M1 = 1<<20, /* Link Sync Cnt wrap MAC 1 */
180 IS_MAC2 = 1<<19, /* IRQ from MAC 2 */
181 IS_LNK_SYNC_M2 = 1<<18, /* Link Sync Cnt wrap MAC 2 */
[all …]
H A Dsky2.h1 /* SPDX-License-Identifier: GPL-2.0 */
30 /* Yukon-2 */
32 PCI_Y2_PIG_ENA = 1<<31, /* Enable Plug-in-Go (YUKON-2) */
33 PCI_Y2_DLL_DIS = 1<<30, /* Disable PCI DLL (YUKON-2) */
34 PCI_SW_PWR_ON_RST= 1<<30, /* SW Power on Reset (Yukon-EX) */
35 PCI_Y2_PHY2_COMA = 1<<29, /* Set PHY 2 to Coma Mode (YUKON-2) */
36 PCI_Y2_PHY1_COMA = 1<<28, /* Set PHY 1 to Coma Mode (YUKON-2) */
37 PCI_Y2_PHY2_POWD = 1<<27, /* Set PHY 2 to Power Down (YUKON-2) */
38 PCI_Y2_PHY1_POWD = 1<<26, /* Set PHY 1 to Power Down (YUKON-2) */
60 /* PCI_OUR_REG_3 32 bit Our Register 3 (Yukon-ECU only) */
[all …]
H A Dsky2.c1 // SPDX-License-Identifier: GPL-2.0-only
7 * of the original driver such as link fail-over and link management because
19 #include <linux/dma-mapping.h>
54 #define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
70 #define RING_NEXT(x, s) (((x)+1) & ((s)-1))
77 static int debug = -1; /* defaults above */
85 static int disable_msi = -1;
94 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
95 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
96 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E01) }, /* SK-9E21M */
[all …]
/linux/drivers/net/usb/
H A Dsmsc95xx.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4 * Copyright (C) 2007-2008 SMSC
38 /* SCSRs - System Control and Status Registers */
52 #define INT_STS_MAC_RTO_ (0x00040000) /* MAC Reset Time Out */
55 #define INT_STS_PHY_INT_ (0x00008000) /* PHY Interrupt */
84 #define HW_CFG_PSEL_ (0x00000004) /* External PHY Select */
106 #define PM_CTL_PHY_RST_ (0x00000010) /* PHY Reset */
126 #define AFC_CFG_HI_ (0x00FF0000) /* Auto Flow Ctrl High Level */
127 #define AFC_CFG_LO_ (0x0000FF00) /* Auto Flow Ctrl Low Level */
129 #define AFC_CFG_FC_MULT_ (0x00000008) /* Flow Ctrl on Mcast Frame */
[all …]
/linux/Documentation/devicetree/bindings/net/
H A Ddavinci_emac.txt7 - compatible: "ti,davinci-dm6467-emac", "ti,am3517-emac" or
8 "ti,dm816-emac"
9 - reg: Offset and length of the register set for the device
10 - ti,davinci-ctrl-reg-offset: offset to control register
11 - ti,davinci-ctrl-mod-reg-offset: offset to control module register
12 - ti,davinci-ctrl-ram-offset: offset to control module ram
13 - ti,davinci-ctrl-ram-size: size of control module ram
14 - interrupts: interrupt mapping for the davinci emac interrupts sources:
21 - phy-handle: See ethernet.txt file in the same directory.
23 - ti,davinci-rmii-en: 1 byte, 1 means use RMII
[all …]
H A Dnixge.txt4 - compatible: Should be "ni,xge-enet-3.00", but can be "ni,xge-enet-2.00" for
5 older device trees with DMA engines co-located in the address map,
7 - reg: Address and length of the register set for the device. It contains the
8 information of registers in the same order as described by reg-names.
9 - reg-names: Should contain the reg names
11 "ctrl": MDIO and PHY control and status region
12 - interrupts: Should contain tx and rx interrupt
13 - interrupt-names: Should be "rx" and "tx"
14 - phy-mode: See ethernet.txt file in the same directory.
15 - nvmem-cells: Phandle of nvmem cell containing the MAC address
[all …]
/linux/drivers/net/ethernet/aeroflex/
H A Dgreth.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Aeroflex Gaisler GRETH 10/100/1G Ethernet MAC.
5 * 2005-2010 (c) Aeroflex Gaisler AB
21 #include <linux/dma-mapping.h>
54 static int greth_debug = -1; /* -1 == use GRETH_DEF_MSG_ENABLE as value */
58 /* Accept MAC address of the form macaddr=0x08,0x00,0x20,0x30,0x40,0x50 */
61 MODULE_PARM_DESC(macaddr, "GRETH Ethernet MAC address");
101 if (skb_shinfo(skb)->nr_frags == 0) in greth_print_tx_packet()
102 length = skb->len; in greth_print_tx_packet()
107 skb->data, length, true); in greth_print_tx_packet()
[all …]
/linux/Documentation/devicetree/bindings/soc/ti/
H A Dti,j721e-system-controller.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: http://devicetree.org/schemas/soc/ti/ti,j721e-system-controller.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
14 represent as any specific type of device. The typical use-case is
15 for some other node's driver, or platform-specific code, to acquire
22 - Kishon Vijay Abraham I <kishon@kernel.org>
23 - Roger Quadros <rogerq@kernel.org>
28 - enum:
[all …]
/linux/drivers/net/ethernet/altera/
H A Daltera_tse_main.c1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Altera Triple-Speed Ethernet MAC driver
3 * Copyright (C) 2008-2014 Altera Corporation. All rights reserved
30 #include <linux/mdio/mdio-regmap.h>
35 #include <linux/pcs-lynx.h>
36 #include <linux/phy.h>
50 static int debug = -1;
52 MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)");
69 #define POLL_PHY (-1)
81 #define TSE_TX_THRESH(x) (x->tx_ring_size / 4)
[all …]
/linux/Documentation/devicetree/bindings/clock/
H A Dingenic,cgu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The CGU in an Ingenic SoC provides all the clocks generated on-chip. It
16 - Paul Cercueil <paul@crapouillou.net>
23 - ingenic,jz4740-cgu
24 - ingenic,jz4725b-cgu
25 - ingenic,jz4755-cgu
26 - ingenic,jz4760-cgu
27 - ingenic,jz4760b-cgu
[all …]
/linux/drivers/net/ethernet/atheros/atlx/
H A Datl2.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright(c) 2006 - 2007 Atheros Corporation. All rights reserved.
4 * Copyright(c) 2007 - 2008 Chris Snook <csnook@redhat.com>
7 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
12 #include <linux/dma-mapping.h>
47 * atl2_pci_tbl - PCI Device ID Table
59 * atl2_sw_init - Initialize general software structures (struct atl2_adapter)
68 struct atl2_hw *hw = &adapter->hw; in atl2_sw_init()
69 struct pci_dev *pdev = adapter->pdev; in atl2_sw_init()
72 hw->vendor_id = pdev->vendor; in atl2_sw_init()
[all …]

123456