Lines Matching +full:mac +full:- +full:phy +full:- +full:ctrl
1 /* SPDX-License-Identifier: GPL-2.0 */
133 CS_CLK_RUN_HOT = 1<<13,/* CLK_RUN hot m. (YUKON-Lite only) */
134 CS_CLK_RUN_RST = 1<<12,/* CLK_RUN reset (YUKON-Lite only) */
135 CS_CLK_RUN_ENA = 1<<11,/* CLK_RUN enable (YUKON-Lite only) */
175 IS_EXT_REG = 1<<23, /* IRQ from LM80 or PHY (GENESIS only) */
176 /* IRQ from PHY (YUKON only) */
178 IS_MAC1 = 1<<21, /* IRQ from MAC 1 */
179 IS_LNK_SYNC_M1 = 1<<20, /* Link Sync Cnt wrap MAC 1 */
180 IS_MAC2 = 1<<19, /* IRQ from MAC 2 */
181 IS_LNK_SYNC_M2 = 1<<18, /* Link Sync Cnt wrap MAC 2 */
221 IS_NO_STAT_M1 = 1<<9, /* No Rx Status from MAC 1 */
222 IS_NO_STAT_M2 = 1<<8, /* No Rx Status from MAC 2 */
223 IS_NO_TIST_M1 = 1<<7, /* No Time Stamp from MAC 1 */
224 IS_NO_TIST_M2 = 1<<6, /* No Time Stamp from MAC 2 */
227 IS_M1_PAR_ERR = 1<<3, /* MAC 1 Parity Error */
228 IS_M2_PAR_ERR = 1<<2, /* MAC 2 Parity Error */
250 /* B2_MAC_CFG 8 bit MAC Configuration / Chip Revision */
254 CFG_DIS_M2_CLK = 1<<1, /* Disable Clock for 2nd MAC */
255 CFG_SNG_MAC = 1<<0, /* MAC Config: 0=2 MACs / 1=1 MAC*/
262 CHIP_ID_YUKON_LITE = 0xb1, /* Chip ID for YUKON-Lite (Rev. A1-A3) */
263 CHIP_ID_YUKON_LP = 0xb2, /* Chip ID for YUKON-LP */
264 CHIP_ID_YUKON_XL = 0xb3, /* Chip ID for YUKON-2 XL */
265 CHIP_ID_YUKON_EC = 0xb6, /* Chip ID for YUKON-2 EC */
266 CHIP_ID_YUKON_FE = 0xb7, /* Chip ID for YUKON-2 FE */
268 CHIP_REV_YU_LITE_A1 = 3, /* Chip Rev. for YUKON-Lite A1,A2 */
269 CHIP_REV_YU_LITE_A3 = 7, /* Chip Rev. for YUKON-Lite A3 */
325 BMU_NO_FCS = 1<<25, /* (Tx) Disable MAC FCS (CRC) generation */
370 /* MAC Arbiter Registers */
371 /* B3_MA_TO_CTRL 16 bit MAC Arbiter Timeout Ctrl Reg */
375 MA_RST_CLR = 1<<1, /* Clear MAC Arbiter Reset */
376 MA_RST_SET = 1<<0, /* Set MAC Arbiter Reset */
381 #define SK_MAC_TO_53 72 /* MAC arbiter timeout */
387 /* B3_PA_CTRL 16 bit Packet Arbiter Ctrl Register */
401 PA_RST_CLR = 1<<1, /* Clear MAC Arbiter Reset */
402 PA_RST_SET = 1<<0, /* Set MAC Arbiter Reset */
409 /* Transmit Arbiter Registers MAC 1 and 2, use SK_REG() to access */
430 * Bank 4 - 5
432 /* Transmit Arbiter Registers MAC 1 and 2, use SK_REG() to access */
489 /* 0x10 - 0x1f: reserved at Tx RAM Buffer Registers */
507 /* Different MAC Types */
513 /* Different PHY Types */
523 /* PHY addresses (bits 12..8 of PHY address reg) */
534 /* Receive MAC FIFO, Receive LED, and Link_Sync regs (GENESIS only) */
536 RX_MFF_EA = 0x0c00,/* 32 bit Receive MAC FIFO End Address */
537 RX_MFF_WP = 0x0c04,/* 32 bit Receive MAC FIFO Write Pointer */
539 RX_MFF_RP = 0x0c0c,/* 32 bit Receive MAC FIFO Read Pointer */
540 RX_MFF_PC = 0x0c10,/* 32 bit Receive MAC FIFO Packet Cnt */
541 RX_MFF_LEV = 0x0c14,/* 32 bit Receive MAC FIFO Level */
542 RX_MFF_CTRL1 = 0x0c18,/* 16 bit Receive MAC FIFO Control Reg 1*/
543 RX_MFF_STAT_TO = 0x0c1a,/* 8 bit Receive MAC Status Timeout */
544 RX_MFF_TIST_TO = 0x0c1b,/* 8 bit Receive MAC Time Stamp Timeout */
545 RX_MFF_CTRL2 = 0x0c1c,/* 8 bit Receive MAC FIFO Control Reg 2*/
546 RX_MFF_TST1 = 0x0c1d,/* 8 bit Receive MAC FIFO Test Reg 1 */
547 RX_MFF_TST2 = 0x0c1e,/* 8 bit Receive MAC FIFO Test Reg 2 */
561 /* Receive and Transmit MAC FIFO Registers (GENESIS only) */
562 /* RX_MFF_CTRL1 16 bit Receive MAC FIFO Control Reg 1 */
581 /* TX_MFF_CTRL1 16 bit Transmit MAC FIFO Control Reg 1 */
600 /* RX_MFF_TST2 8 bit Receive MAC FIFO Test Register 2 */
601 /* TX_MFF_TST2 8 bit Transmit MAC FIFO Test Register 2 */
612 /* RX_MFF_TST1 8 bit Receive MAC FIFO Test Register 1 */
613 /* TX_MFF_TST1 8 bit Transmit MAC FIFO Test Register 1 */
624 /* RX_MFF_CTRL2 8 bit Receive MAC FIFO Control Reg 2 */
625 /* TX_MFF_CTRL2 8 bit Transmit MAC FIFO Control Reg 2 */
629 MFF_RST_CLR = 1<<1, /* Clear MAC FIFO Reset */
630 MFF_RST_SET = 1<<0, /* Set MAC FIFO Reset */
697 /* B0_R1_CSR 32 bit BMU Ctrl/Stat Rx Queue 1 */
698 /* B0_R2_CSR 32 bit BMU Ctrl/Stat Rx Queue 2 */
699 /* B0_XA1_CSR 32 bit BMU Ctrl/Stat Sync Tx Queue 1 */
700 /* B0_XS1_CSR 32 bit BMU Ctrl/Stat Async Tx Queue 1 */
701 /* B0_XA2_CSR 32 bit BMU Ctrl/Stat Sync Tx Queue 2 */
702 /* B0_XS2_CSR 32 bit BMU Ctrl/Stat Async Tx Queue 2 */
776 /* Transmit MAC FIFO and Transmit LED Registers (GENESIS only), */
778 TX_MFF_EA = 0x0d00,/* 32 bit Transmit MAC FIFO End Address */
779 TX_MFF_WP = 0x0d04,/* 32 bit Transmit MAC FIFO WR Pointer */
780 TX_MFF_WSP = 0x0d08,/* 32 bit Transmit MAC FIFO WR Shadow Ptr */
781 TX_MFF_RP = 0x0d0c,/* 32 bit Transmit MAC FIFO RD Pointer */
782 TX_MFF_PC = 0x0d10,/* 32 bit Transmit MAC FIFO Packet Cnt */
783 TX_MFF_LEV = 0x0d14,/* 32 bit Transmit MAC FIFO Level */
784 TX_MFF_CTRL1 = 0x0d18,/* 16 bit Transmit MAC FIFO Ctrl Reg 1 */
785 TX_MFF_WAF = 0x0d1a,/* 8 bit Transmit MAC Wait after flush */
787 TX_MFF_CTRL2 = 0x0d1c,/* 8 bit Transmit MAC FIFO Ctrl Reg 2 */
788 TX_MFF_TST1 = 0x0d1d,/* 8 bit Transmit MAC FIFO Test Reg 1 */
789 TX_MFF_TST2 = 0x0d1e,/* 8 bit Transmit MAC FIFO Test Reg 2 */
828 B28_DPT_CTRL = 0x0e08,/* 8 bit Descriptor Poll Timer Ctrl Reg */
834 GMAC_TI_ST_CTRL = 0x0e18,/* 8 bit Time Stamp Timer Ctrl Reg */
856 /* Wake-up Frame Pattern Match Control Registers (YUKON only) */
858 WOL_REG_OFFS = 0x20,/* HW-Bug: Address is + 0x20 against spec. */
863 WOL_MAC_ADDR = 0x0f24,/* 32 bit WOL MAC Address */
908 XMR_FS_LEN_ERR = 1<<6, /* Bit 6: In-Range Length Error */
914 XMR_FS_MCTRL = 1<<0, /* Bit 0: MAC Control Packet */
927 ,* XMAC-PHY Registers, indirect addressed over the XMAC
930 PHY_XMAC_CTRL = 0x00,/* 16 bit r/w PHY Control Register */
931 PHY_XMAC_STAT = 0x01,/* 16 bit r/w PHY Status Register */
932 PHY_XMAC_ID0 = 0x02,/* 16 bit r/o PHY ID0 Register */
933 PHY_XMAC_ID1 = 0x03,/* 16 bit r/o PHY ID1 Register */
934 PHY_XMAC_AUNE_ADV = 0x04,/* 16 bit r/w Auto-Neg. Advertisement */
936 PHY_XMAC_AUNE_EXP = 0x06,/* 16 bit r/o Auto-Neg. Expansion Reg */
941 PHY_XMAC_RES_ABI = 0x10,/* 16 bit r/o PHY Resolved Ability */
944 * Broadcom-PHY Registers, indirect addressed over XMAC
947 PHY_BCOM_CTRL = 0x00,/* 16 bit r/w PHY Control Register */
948 PHY_BCOM_STAT = 0x01,/* 16 bit r/o PHY Status Register */
949 PHY_BCOM_ID0 = 0x02,/* 16 bit r/o PHY ID0 Register */
950 PHY_BCOM_ID1 = 0x03,/* 16 bit r/o PHY ID1 Register */
951 PHY_BCOM_AUNE_ADV = 0x04,/* 16 bit r/w Auto-Neg. Advertisement */
953 PHY_BCOM_AUNE_EXP = 0x06,/* 16 bit r/o Auto-Neg. Expansion Reg */
956 /* Broadcom-specific registers */
957 PHY_BCOM_1000T_CTRL = 0x09,/* 16 bit r/w 1000Base-T Control Reg */
958 PHY_BCOM_1000T_STAT = 0x0a,/* 16 bit r/o 1000Base-T Status Reg */
960 PHY_BCOM_P_EXT_CTRL = 0x10,/* 16 bit r/w PHY Extended Ctrl Reg */
961 PHY_BCOM_P_EXT_STAT = 0x11,/* 16 bit r/o PHY Extended Stat Reg */
973 * Marvel-PHY Registers, indirect addressed over GMAC
976 PHY_MARV_CTRL = 0x00,/* 16 bit r/w PHY Control Register */
977 PHY_MARV_STAT = 0x01,/* 16 bit r/o PHY Status Register */
978 PHY_MARV_ID0 = 0x02,/* 16 bit r/o PHY ID0 Register */
979 PHY_MARV_ID1 = 0x03,/* 16 bit r/o PHY ID1 Register */
980 PHY_MARV_AUNE_ADV = 0x04,/* 16 bit r/w Auto-Neg. Advertisement */
982 PHY_MARV_AUNE_EXP = 0x06,/* 16 bit r/o Auto-Neg. Expansion Reg */
985 /* Marvel-specific registers */
986 PHY_MARV_1000T_CTRL = 0x09,/* 16 bit r/w 1000Base-T Control Reg */
987 PHY_MARV_1000T_STAT = 0x0a,/* 16 bit r/o 1000Base-T Status Reg */
989 PHY_MARV_PHY_CTRL = 0x10,/* 16 bit r/w PHY Specific Ctrl Reg */
990 PHY_MARV_PHY_STAT = 0x11,/* 16 bit r/o PHY Specific Stat Reg */
993 PHY_MARV_EXT_CTRL = 0x14,/* 16 bit r/w Ext. PHY Specific Ctrl */
999 PHY_MARV_EXT_CTRL_2 = 0x1a,/* 16 bit r/w Ext. PHY Specific Ctrl 2 */
1000 PHY_MARV_EXT_P_STAT = 0x1b,/* 16 bit r/w Ext. PHY Spec. Stat Reg */
1005 /* for 10/100 Fast Ethernet PHY (88E3082 only) */
1014 PHY_CT_RESET = 1<<15, /* Bit 15: (sc) clear all PHY related regs */
1015 PHY_CT_LOOP = 1<<14, /* Bit 14: enable Loopback over PHY */
1017 PHY_CT_ANE = 1<<12, /* Bit 12: Auto-Negotiation Enabled */
1020 PHY_CT_RE_CFG = 1<<9, /* Bit 9: (sc) Restart Auto-Negotiation */
1036 PHY_ST_AN_OVER = 1<<5, /* Bit 5: Auto-Negotiation Over */
1038 PHY_ST_AN_CAP = 1<<3, /* Bit 3: Auto-Negotiation Capability */
1050 /* different Broadcom PHY Ids */
1058 /* different Marvell PHY Ids */
1061 PHY_MARV_ID1_B0 = 0x0C23, /* Yukon (PHY 88E1011) */
1062 PHY_MARV_ID1_B2 = 0x0C25, /* Yukon-Plus (PHY 88E1011) */
1063 PHY_MARV_ID1_C2 = 0x0CC2, /* Yukon-EC (PHY 88E1111) */
1064 PHY_MARV_ID1_Y2 = 0x0C91, /* Yukon-2 (PHY 88E1112) */
1076 PHY_AN_100FULL = 1<<8, /* Bit 8: Try for 100mbps full-duplex */
1077 PHY_AN_100HALF = 1<<7, /* Bit 7: Try for 100mbps half-duplex */
1078 PHY_AN_10FULL = 1<<6, /* Bit 6: Try for 10mbps full-duplex */
1079 PHY_AN_10HALF = 1<<5, /* Bit 5: Try for 10mbps half-duplex */
1113 /***** PHY_XMAC_RES_ABI 16 bit r/o PHY Resolved Ability *****/
1127 X_RFB_AN_ERR = 3<<12,/* Bit 13..12 Auto-Negotiation Error */
1130 /* Broadcom-Specific */
1131 /***** PHY_BCOM_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/
1141 /***** PHY_BCOM_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/
1142 /***** PHY_MARV_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/
1156 PHY_B_ES_X_FD_CAP = 1<<15, /* Bit 15: 1000Base-X FD capable */
1157 PHY_B_ES_X_HD_CAP = 1<<14, /* Bit 14: 1000Base-X HD capable */
1158 PHY_B_ES_T_FD_CAP = 1<<13, /* Bit 13: 1000Base-T FD capable */
1159 PHY_B_ES_T_HD_CAP = 1<<12, /* Bit 12: 1000Base-T HD capable */
1162 /***** PHY_BCOM_P_EXT_CTRL 16 bit r/w PHY Extended Control Reg *****/
1164 PHY_B_PEC_MAC_PHY = 1<<15, /* Bit 15: 10BIT/GMI-Interface */
1169 PHY_B_PEC_BY_45 = 1<<10, /* Bit 10: Bypass 4B5B-Decoder */
1182 /***** PHY_BCOM_P_EXT_STAT 16 bit r/o PHY Extended Status Reg *****/
1200 /* PHY_BCOM_AUNE_ADV 16 bit r/w Auto-Negotiation Advertisement *****/
1246 PHY_B_AS_PRR = 1<<1, /* Bit 1: Pause Resolution-Rx */
1247 PHY_B_AS_PRT = 1<<0, /* Bit 0: Pause Resolution-Tx */
1285 PHY_B_RES_1000FD = 7<<8,/* Bit 10..8: 1000Base-T Full Dup. */
1286 PHY_B_RES_1000HD = 6<<8,/* Bit 10..8: 1000Base-T Half Dup. */
1289 /** Marvell-Specific */
1296 PHY_M_AN_PC = 1<<10, /* MAC Pause implemented */
1297 PHY_M_AN_100_T4 = 1<<9, /* Not cap. 100Base-T4 (always 0) */
1298 PHY_M_AN_100_FD = 1<<8, /* Advertise 100Base-TX Full Duplex */
1299 PHY_M_AN_100_HD = 1<<7, /* Advertise 100Base-TX Half Duplex */
1300 PHY_M_AN_10_FD = 1<<6, /* Advertise 10Base-TX Full Duplex */
1301 PHY_M_AN_10_HD = 1<<5, /* Advertise 10Base-TX Half Duplex */
1308 PHY_M_AN_PC_X = 1<<7, /* MAC Pause implemented */
1309 PHY_M_AN_1000X_AHD = 1<<6, /* Advertise 10000Base-X Half Duplex */
1310 PHY_M_AN_1000X_AFD = 1<<5, /* Advertise 10000Base-X Full Duplex */
1321 /***** PHY_MARV_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/
1326 PHY_M_1000C_MPD = 1<<10, /* Multi-Port Device */
1331 /***** PHY_MARV_PHY_CTRL 16 bit r/w PHY Specific Ctrl Reg *****/
1341 PHY_M_PC_MAC_POW_UP = 1<<3, /* MAC Power up */
1358 /* for 10/100 Fast Ethernet PHY (88E3082 only) */
1373 /***** PHY_MARV_PHY_STAT 16 bit r/o PHY Specific Status Reg *****/
1395 /* for 10/100 Fast Ethernet PHY (88E3082 only) */
1402 PHY_M_IS_AN_ERROR = 1<<15, /* Auto-Negotiation Error */
1406 PHY_M_IS_AN_COMPL = 1<<11, /* Auto-Negotiation Completed */
1425 /***** PHY_MARV_EXT_CTRL 16 bit r/w Ext. PHY Specific Ctrl *****/
1440 PHY_M_EC_MAC_S_MSK = 7<<4, /* Bit 6.. 4: Def. MAC interface speed */
1441 PHY_M_EC_FIB_AN_ENA = 1<<3, /* Fiber Auto-Neg. Enable (88E1011S only) */
1519 /***** PHY_MARV_EXT_CTRL_2 16 bit r/w Ext. PHY Specific Ctrl 2 *****/
1528 /***** PHY_MARV_EXT_P_STAT 16 bit r/w Ext. PHY Specific Status *****/
1563 /* for 10/100 Fast Ethernet PHY (88E3082 only) */
1598 PHY_M_FESC_ENA_MCLK = 1<<1, /* Enable MAC Rx Clock in sleep mode */
1599 PHY_M_FESC_SEL_CL_A = 1<<0, /* Select Class A driver (100B-TX) */
1605 PHY_M_LEDC_LOS_MSK = 0xf<<12, /* Bit 15..12: LOS LED Ctrl. Mask */
1606 PHY_M_LEDC_INIT_MSK = 0xf<<8, /* Bit 11.. 8: INIT LED Ctrl. Mask */
1607 PHY_M_LEDC_STA1_MSK = 0xf<<4, /* Bit 7.. 4: STAT1 LED Ctrl. Mask */
1608 PHY_M_LEDC_STA0_MSK = 0xf, /* Bit 3.. 0: STAT0 LED Ctrl. Mask */
1623 GM_TX_FLOW_CTRL = 0x0010, /* 16 bit r/w Transmit Flow-Control */
1661 * MIB Counters base address definitions (low word) -
1667 GM_RXF_MPAUSE = GM_MIB_CNT_BASE + 16, /* Pause MAC Ctrl Frames Received */
1678 GM_RXF_127B = GM_MIB_CNT_BASE + 104, /* 65-127 Byte Rx Frame */
1679 GM_RXF_255B = GM_MIB_CNT_BASE + 112, /* 128-255 Byte Rx Frame */
1680 GM_RXF_511B = GM_MIB_CNT_BASE + 120, /* 256-511 Byte Rx Frame */
1681 GM_RXF_1023B = GM_MIB_CNT_BASE + 128, /* 512-1023 Byte Rx Frame */
1682 GM_RXF_1518B = GM_MIB_CNT_BASE + 136, /* 1024-1518 Byte Rx Frame */
1683 GM_RXF_MAX_SZ = GM_MIB_CNT_BASE + 144, /* 1519-MaxSize Byte Rx Frame */
1691 GM_TXF_MPAUSE = GM_MIB_CNT_BASE + 208, /* Pause MAC Ctrl Frames Xmitted */
1696 GM_TXF_127B = GM_MIB_CNT_BASE + 248, /* 65-127 Byte Tx Frame */
1697 GM_TXF_255B = GM_MIB_CNT_BASE + 256, /* 128-255 Byte Tx Frame */
1698 GM_TXF_511B = GM_MIB_CNT_BASE + 264, /* 256-511 Byte Tx Frame */
1699 GM_TXF_1023B = GM_MIB_CNT_BASE + 272, /* 512-1023 Byte Tx Frame */
1700 GM_TXF_1518B = GM_MIB_CNT_BASE + 280, /* 1024-1518 Byte Tx Frame */
1701 GM_TXF_MAX_SZ = GM_MIB_CNT_BASE + 288, /* 1519-MaxSize Byte Tx Frame */
1716 GM_GPSR_FC_TX_DIS = 1<<13, /* Bit 13: Tx Flow-Control Mode Disabled */
1723 GM_GPSR_PHY_ST_CH = 1<<5, /* Bit 5: PHY Status Change */
1726 GM_GPSR_FC_RX_DIS = 1<<2, /* Bit 2: Rx Flow-Control Mode Disabled */
1733 GM_GPCR_FC_TX_DIS = 1<<13, /* Bit 13: Disable Tx Flow-Control Mode */
1737 GM_GPCR_LOOP_ENA = 1<<9, /* Bit 9: Enable MAC Loopback Mode */
1742 GM_GPCR_FC_RX_DIS = 1<<4, /* Bit 4: Disable Rx Flow-Control Mode */
1744 GM_GPCR_AU_DUP_DIS = 1<<2, /* Bit 2: Disable Auto-Update Duplex */
1745 GM_GPCR_AU_FCT_DIS = 1<<1, /* Bit 1: Disable Auto-Update Flow-C. */
1746 GM_GPCR_AU_SPD_DIS = 1<<0, /* Bit 0: Disable Auto-Update Speed */
1754 GM_TXCR_FORCE_JAM = 1<<15, /* Bit 15: Force Jam / Flow-Control */
1767 GM_RXCR_CRC_DIS = 1<<13, /* Bit 13: Remove 4-byte CRC */
1793 GM_SMOD_IPG_MSK = 0x1f /* Bit 4..0: Inter-Packet Gap (IPG) */
1804 GM_SMI_CT_PHY_A_MSK = 0x1f<<11, /* Bit 15..11: PHY Device Address */
1805 GM_SMI_CT_REG_A_MSK = 0x1f<<6, /* Bit 10.. 6: PHY Register Address */
1830 GMR_FS_GOOD_FC = 1<<7, /* Bit 7: Good Flow-Control Packet */
1831 GMR_FS_BAD_FC = 1<<6, /* Bit 6: Bad Flow-Control Packet */
1883 /* GMAC_TI_ST_CTRL 8 bit Time Stamp Timer Ctrl Reg (YUKON only) */
1904 GPC_SEL_BDT = 1<<28, /* Select Bi-Dir. Transfer for MDC/MDIO */
1920 GPC_PHYADDR_4 = 1<<12, /* Bit 4 of Phy Addr */
1921 GPC_PHYADDR_3 = 1<<11, /* Bit 3 of Phy Addr */
1922 GPC_PHYADDR_2 = 1<<10, /* Bit 2 of Phy Addr */
1923 GPC_PHYADDR_1 = 1<<9, /* Bit 1 of Phy Addr */
1924 GPC_PHYADDR_0 = 1<<8, /* Bit 0 of Phy Addr */
1940 /* auto-negotiation with limited advertised speeds */
2014 XM_PHY_ADDR = 0x0034, /* 16 bit r/w PHY Address Register */
2015 XM_PHY_DATA = 0x0038, /* 16 bit r/w PHY Data Register */
2026 XM_MAC_OPCODE = 0x0074, /* 16 bit r/w Opcode for MAC control frames */
2027 XM_MAC_PTIME = 0x0076, /* 16 bit r/w Pause time for MAC ctrl frames*/
2059 XM_TXF_MPAUSE = 0x02a0, /* 32 bit r/o Tx Pause MAC Ctrl Frame Cnt */
2060 XM_TXF_MCTRL = 0x02a4, /* 32 bit r/o Tx MAC Ctrl Frame Counter */
2071 XM_TXF_127B = 0x02d4, /* 32 bit r/o 65-127 Byte Tx Frame Counter */
2072 XM_TXF_255B = 0x02d8, /* 32 bit r/o 128-255 Byte Tx Frame Counter */
2073 XM_TXF_511B = 0x02dc, /* 32 bit r/o 256-511 Byte Tx Frame Counter */
2074 XM_TXF_1023B = 0x02e0, /* 32 bit r/o 512-1023 Byte Tx Frame Counter*/
2075 XM_TXF_MAX_SZ = 0x02e4, /* 32 bit r/o 1024-MaxSize Byte Tx Frame Cnt*/
2082 XM_RXF_MPAUSE = 0x0318, /* 32 bit r/o Rx Pause MAC Ctrl Frame Cnt */
2083 XM_RXF_MCTRL = 0x031c, /* 32 bit r/o Rx MAC Ctrl Frame Counter */
2085 XM_RXF_INV_MOC = 0x0324, /* 32 bit r/o Rx Frames with inv. MAC Opcode*/
2101 XM_RXF_127B = 0x036c, /* 32 bit r/o 65-127 Byte Rx Frame Counter */
2102 XM_RXF_255B = 0x0370, /* 32 bit r/o 128-255 Byte Rx Frame Counter */
2103 XM_RXF_511B = 0x0374, /* 32 bit r/o 256-511 Byte Rx Frame Counter */
2104 XM_RXF_1023B = 0x0378, /* 32 bit r/o 512-1023 Byte Rx Frame Counter*/
2105 XM_RXF_MAX_SZ = 0x037c, /* 32 bit r/o 1024-MaxSize Byte Rx Frame Cnt*/
2110 XM_MMU_PHY_RDY = 1<<12, /* Bit 12: PHY Read Ready */
2111 XM_MMU_PHY_BUSY = 1<<11, /* Bit 11: PHY Busy */
2113 XM_MMU_MAC_LB = 1<<9, /* Bit 9: Enable MAC Loopback */
2119 XM_MMU_GMII_LOOP= 1<<2, /* Bit 2: PHY is in Loopback Mode */
2166 XM_GP_ANIP = 1<<6, /* Bit 6: (ro) Auto-Neg. in progress */
2168 XM_GP_RES_MAC = 1<<3, /* Bit 3: (sc) Reset MAC and FIFOs */
2184 XM_IS_AND = 1<<7, /* Bit 7: Auto-Negotiation Done */
2263 XM_MD_RX_MCTRL = 1<<12, /* Bit 12: Rx MAC Control Frame */
2296 XMR_MAX_SZ_OV = 1<<31, /* Bit 31: 1024-MaxSize Rx Cnt Ov*/
2297 XMR_1023B_OV = 1<<30, /* Bit 30: 512-1023Byte Rx Cnt Ov*/
2298 XMR_511B_OV = 1<<29, /* Bit 29: 256-511 Byte Rx Cnt Ov*/
2299 XMR_255B_OV = 1<<28, /* Bit 28: 128-255 Byte Rx Cnt Ov*/
2300 XMR_127B_OV = 1<<27, /* Bit 27: 65-127 Byte Rx Cnt Ov */
2316 XMR_INV_MOC = 1<<9, /* Bit 9: Rx with inv. MAC OC Ov*/
2318 XMR_MCTRL_OV = 1<<7, /* Bit 7: Rx MAC Ctrl-F Cnt Ov */
2319 XMR_MPAUSE_OV = 1<<6, /* Bit 6: Rx Pause MAC Ctrl-F Ov*/
2333 XMT_MAX_SZ_OV = 1<<25, /* Bit 25: 1024-MaxSize Tx Cnt Ov*/
2334 XMT_1023B_OV = 1<<24, /* Bit 24: 512-1023Byte Tx Cnt Ov*/
2335 XMT_511B_OV = 1<<23, /* Bit 23: 256-511 Byte Tx Cnt Ov*/
2336 XMT_255B_OV = 1<<22, /* Bit 22: 128-255 Byte Tx Cnt Ov*/
2337 XMT_127B_OV = 1<<21, /* Bit 21: 65-127 Byte Tx Cnt Ov */
2349 XMT_MCTRL_OV = 1<<9, /* Bit 9: Tx MAC Ctrl Counter Ov*/
2350 XMT_MPAUSE = 1<<8, /* Bit 8: Tx Pause MAC Ctrl-F Ov*/
2427 FLOW_MODE_NONE = 1, /* No Flow-Control */
2478 return readl(hw->regs + reg); in skge_read32()
2483 return readw(hw->regs + reg); in skge_read16()
2488 return readb(hw->regs + reg); in skge_read8()
2493 writel(val, hw->regs + reg); in skge_write32()
2498 writew(val, hw->regs + reg); in skge_write16()
2503 writeb(val, hw->regs + reg); in skge_write8()
2506 /* MAC Related Registers inside the device. */
2509 ((BASE_XMAC_1 + (port) * (BASE_XMAC_2 - BASE_XMAC_1)) | (reg) << 1)
2553 (BASE_GMAC_1 + (port) * (BASE_GMAC_2-BASE_GMAC_1) + (reg))