| /linux/tools/perf/pmu-events/arch/arm64/ampere/ampereonex/ |
| H A D | core-imp-def.json | 3 "PublicDescription": "Level 2 prefetch requests, refilled to L2 cache",
6 "BriefDescription": "Level 2 prefetch requests, refilled to L2 cache"
9 "PublicDescription": "Level 2 prefetch requests, late",
12 "BriefDescription": "Level 2 prefetch requests, late"
15 "PublicDescription": "Predictable branch speculatively executed that hit any level of BTB",
18 "BriefDescription": "Predictable branch speculatively executed that hit any level of BTB"
21 …licDescription": "Predictable conditional branch speculatively executed that hit any level of BTB",
24 …riefDescription": "Predictable conditional branch speculatively executed that hit any level of BTB"
27 …"PublicDescription": "Predictable taken branch speculatively executed that hit any level of BTB th…
30 …"BriefDescription": "Predictable taken branch speculatively executed that hit any level of BTB tha…
[all …]
|
| /linux/tools/perf/pmu-events/arch/arm64/ampere/ampereone/ |
| H A D | core-imp-def.json | 3 "PublicDescription": "Level 2 prefetch requests, refilled to L2 cache",
6 "BriefDescription": "Level 2 prefetch requests, refilled to L2 cache"
9 "PublicDescription": "Level 2 prefetch requests, late",
12 "BriefDescription": "Level 2 prefetch requests, late"
15 "PublicDescription": "Predictable branch speculatively executed that hit any level of BTB",
18 "BriefDescription": "Predictable branch speculatively executed that hit any level of BTB"
21 …licDescription": "Predictable conditional branch speculatively executed that hit any level of BTB",
24 …riefDescription": "Predictable conditional branch speculatively executed that hit any level of BTB"
27 …"PublicDescription": "Predictable taken branch speculatively executed that hit any level of BTB th…
30 …"BriefDescription": "Predictable taken branch speculatively executed that hit any level of BTB tha…
[all …]
|
| /linux/Documentation/devicetree/bindings/interrupt-controller/ |
| H A D | img,pdc-intc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/img,pdc-intc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - James Hogan <jhogan@kernel.org>
19 const: img,pdc-intc
24 interrupt-controller: true
26 '#interrupt-cells':
28 <1st-cell>: The interrupt-number that identifies the interrupt source.
29 0-7: Peripheral interrupts
[all …]
|
| H A D | arm,gic-v5-iwb.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic-v5-iwb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lpieralisi@kernel.org>
11 - Marc Zyngier <maz@kernel.org>
24 - $ref: /schemas/interrupt-controller.yaml#
28 const: arm,gic-v5-iwb
32 - description: IWB control frame
34 "#address-cells":
[all …]
|
| H A D | interrupts.txt | 5 -------------------------
8 "interrupts" property, an "interrupts-extended" property, or both. If both are
16 interrupt-parent = <&intc1>;
19 The "interrupt-parent" property is used to specify the controller to which
25 The "interrupts-extended" property is a special form; useful when a node needs
31 interrupts-extended = <&intc1 5 1>, <&intc2 1 0>;
34 -----------------------------
36 A device is marked as an interrupt controller with the "interrupt-controller"
37 property. This is a empty, boolean property. An additional "#interrupt-cells"
45 -----------
[all …]
|
| H A D | snps,archs-idu-intc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/snps,archs-idu-intc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARC-HS Interrupt Distribution Unit
10 - Vineet Gupta <vgupta@kernel.org>
13 ARC-HS Interrupt Distribution Unit is an optional 2nd level interrupt
22 const: snps,archs-idu-intc
24 interrupt-controller: true
26 '#interrupt-cells':
[all …]
|
| /linux/Documentation/devicetree/bindings/power/reset/ |
| H A D | gpio-restart.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/power/reset/gpio-restart.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sebastian Reichel <sre@kernel.org>
15 This binding supports level and edge triggered reset. At driver load time, the driver will
17 'open-source' is not found, the GPIO line will be driven in the inactive state. Otherwise its
21 is configured as an output, and driven active, triggering a level triggered reset condition.
22 This will also cause an inactive->active edge condition, triggering positive edge triggered
23 reset. After a delay specified by active-delay, the GPIO is set to inactive, thus causing an
[all …]
|
| /linux/arch/loongarch/include/asm/ |
| H A D | kvm_pch_pic.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
59 uint64_t edge; /* 1:edge triggered, 0:level triggered */
65 uint64_t polarity; /* 0: high level trigger, 1: low level trigger */
74 void pch_pic_set_irq(struct loongarch_pch_pic *s, int irq, int level);
75 int pch_msi_set_irq(struct kvm *kvm, struct kvm_kernel_irq_routing_entry *e, int level);
|
| /linux/Documentation/virt/kvm/devices/ |
| H A D | arm-vgic-v3.rst | 1 .. SPDX-License-Identifier: GPL-2.0
9 - KVM_DEV_TYPE_ARM_VGIC_V3 ARM Generic Interrupt Controller v3.0
12 will act as the VM interrupt controller, requiring emulated user-space devices
24 KVM_VGIC_V3_ADDR_TYPE_DIST (rw, 64-bit)
29 KVM_VGIC_V3_ADDR_TYPE_REDIST (rw, 64-bit)
36 KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION (rw, 64-bit)
39 bits: | 63 .... 52 | 51 .... 16 | 15 - 12 |11 - 0
42 - index encodes the unique redistributor region index
43 - flags: reserved for future use, currently 0
44 - base field encodes bits [51:16] of the guest physical base address
[all …]
|
| /linux/Documentation/devicetree/bindings/leds/backlight/ |
| H A D | mediatek,mt6370-backlight.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/leds/backlight/mediatek,mt6370-backlight.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - ChiaEn Wu <chiaen_wu@richtek.com>
21 - $ref: common.yaml#
26 - mediatek,mt6370-backlight
27 - mediatek,mt6372-backlight
29 default-brightness:
32 max-brightness:
[all …]
|
| /linux/arch/mips/include/asm/ |
| H A D | mips-gic.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
8 # error Please include asm/mips-cps.h rather than asm/mips-gic.h
29 /* For read-only shared registers */
34 /* For read-write shared registers */
39 /* For read-only local registers */
44 /* For read-write local registers */
49 /* For read-only shared per-interrupt registers */
62 /* For read-write shared per-interrupt registers */
81 /* For read-only local per-interrupt registers */
88 /* For read-write local per-interrupt registers */
[all …]
|
| /linux/Documentation/devicetree/bindings/pinctrl/ |
| H A D | pinctrl-st.txt | 3 Each multi-function pin is controlled, driven and routed through the
5 and multiple alternate functions(ALT1 - ALTx) that directly connect
14 GPIO bank can have one of the two possible types of interrupt-wirings.
20 | |----> [gpio-bank (n) ]
21 | |----> [gpio-bank (n + 1)]
22 [irqN]-- | irq-mux |----> [gpio-bank (n + 2)]
23 | |----> [gpio-bank (... )]
24 |_________|----> [gpio-bank (n + 7)]
28 [irqN]----> [gpio-bank (n)]
33 - compatible : should be "st,stih407-<pio-block>-pinctrl"
[all …]
|
| /linux/Documentation/devicetree/bindings/gpio/ |
| H A D | nvidia,tegra20-gpio.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/nvidia,tegra20-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra GPIO Controller (Tegra20 - Tegra210)
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
16 - enum:
17 - nvidia,tegra20-gpio
18 - nvidia,tegra30-gpio
[all …]
|
| H A D | socionext,uniphier-gpio.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/gpio/socionext,uniphier-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Masahiro Yamada <yamada.masahiro@socionext.com>
14 pattern: "^gpio@[0-9a-f]+$"
17 const: socionext,uniphier-gpio
22 gpio-controller: true
24 "#gpio-cells":
27 interrupt-controller: true
[all …]
|
| H A D | sodaville.txt | 14 - <1st cell>: The interrupt-number that identifies the interrupt source.
15 - <2nd cell>: The level-sense information, encoded as follows:
16 4 - active high level-sensitive
17 8 - active low level-sensitive
23 #gpio-cells = <2>;
24 #interrupt-cells = <2>;
34 interrupt-controller;
35 gpio-controller;
41 /* User the 11th GPIO line as an active high triggered
42 * level interrupt
[all …]
|
| /linux/Documentation/process/ |
| H A D | threat-model.rst | 6 (:doc:`security-related ones <security-bugs>` vs :doc:`non-security ones
7 <../admin-guide/reporting-issues>`), and can complicate security enforcement
15 -----------------------------
20 a level of confidentiality to their communications and to the data they are
26 of the Memory Management Unit (MMU), the isolation of DMA-capable peripherals
31 side-channels, hardware response to unexpected inputs), the kernel will usually
32 attempt to implement reasonable mitigations. These are best-effort measures
35 kernel-provided safety guarantee.
39 users benefit from available resources, or the level of confidentiality of
42 is performed via configuration (sysctl, file-system permissions etc).
[all …]
|
| /linux/drivers/pinctrl/starfive/ |
| H A D | pinctrl-starfive-jh7100.c | 1 // SPDX-License-Identifier: GPL-2.0
25 #include <dt-bindings/pinctrl/pinctrl-starfive-jh7100.h>
28 #include "../pinctrl-utils.h"
32 #define DRIVER_NAME "pinctrl-starfive"
36 * https://github.com/starfive-tech/JH7100_Docs
47 * The following 32-bit registers come in pairs, but only the offset of the
48 * first register is defined. The first controls (interrupts for) GPIO 0-31 and
49 * the second GPIO 32-63.
53 * Interrupt Type. If set to 1 the interrupt is edge-triggered. If set to 0 the
54 * interrupt is level-triggered.
[all …]
|
| /linux/Documentation/hwmon/ |
| H A D | lm78.rst | 6 * National Semiconductor LM78 / LM78-J
10 Addresses scanned: I2C 0x28 - 0x2f, ISA 0x290 (8 I/O ports)
20 Addresses scanned: I2C 0x28 - 0x2f, ISA 0x290 (8 I/O ports)
28 - Frodo Looijaard <frodol@dds.nl>
29 - Jean Delvare <jdelvare@suse.de>
32 -----------
34 This driver implements support for the National Semiconductor LM78, LM78-J
38 the LM78 and LM78-J are exactly identical. The LM79 has one more VID line,
45 Temperatures are measured in degrees Celsius. An alarm is triggered once
46 when the Overtemperature Shutdown limit is crossed; it is triggered again
[all …]
|
| /linux/Documentation/bpf/ |
| H A D | prog_cgroup_sockopt.rst | 1 .. SPDX-License-Identifier: GPL-2.0
10 * ``BPF_CGROUP_GETSOCKOPT`` - called every time process executes ``getsockopt``
12 * ``BPF_CGROUP_SETSOCKOPT`` - called every time process executes ``setsockopt``
16 all input arguments: ``level``, ``optname``, ``optval`` and ``optlen``.
21 ``BPF_CGROUP_SETSOCKOPT`` is triggered *before* the kernel handling of
26 If BPF program sets ``optlen`` to -1, the control will be returned
30 Note, that ``optlen`` can not be increased beyond the user-supplied
31 value. It can only be decreased or set to -1. Any other value will
35 -----------
37 * ``0`` - reject the syscall, ``EPERM`` will be returned to the userspace.
[all …]
|
| /linux/Documentation/driver-api/gpio/ |
| H A D | intro.rst | 17 A "General Purpose Input/Output" (GPIO) is a flexible software-controlled
25 System-on-Chip (SOC) processors heavily rely on GPIOs. In some cases, every
26 non-dedicated pin can be configured as a GPIO; and most chips have at least
31 Most PC southbridges have a few dozen GPIO-capable pins (with only the BIOS
36 - Output values are writable (high=1, low=0). Some chips also have
38 value might be driven, supporting "wire-OR" and similar schemes for the
41 - Input values are likewise readable (1, 0). Some chips support readback
42 of pins configured as "output", which is very useful in such "wire-OR"
44 input de-glitch/debounce logic, sometimes with software controls.
46 - Inputs can often be used as IRQ signals, often edge triggered but
[all …]
|
| /linux/drivers/gpu/drm/amd/include/ivsrcid/dcn/ |
| H A D | irqsrcs_dcn_1_0.h | 30 …C_I2C_SW_DONE 1 // DC_I2C SW done DC_I2C_SW_DONE_INTERRUPT DISP_INTERRUPT_STATUS Level
33 … // DC_I2C DDC1 HW done DOUT_IHC_I2C_DDC1_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level
36 … // DC_I2C DDC2 HW done DOUT_IHC_I2C_DDC2_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level
39 … // DC_I2C DDC3 HW done DOUT_IHC_I2C_DDC3_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level
42 … // DC_I2C_DDC4 HW done DOUT_IHC_I2C_DDC4_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level
45 … // DC_I2C_DDC5 HW done DOUT_IHC_I2C_DDC5_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level
48 … // DC_I2C_DDC6 HW done DOUT_IHC_I2C_DDC6_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level
51 …DC_I2C_DDCVGA HW done DOUT_IHC_I2C_DDCVGA_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level
54 …DC1 read request DC_I2C_DDC1_READ_REQUEST_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level / Pulse
57 …DC2 read request DC_I2C_DDC2_READ_REQUEST_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level / Pulse
[all …]
|
| /linux/drivers/gpio/ |
| H A D | gpio-adnp.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2011-2012 Avionic Design GmbH
16 #define GPIO_DDR(gpio) (0x00 << (gpio)->reg_shift)
17 #define GPIO_PLR(gpio) (0x01 << (gpio)->reg_shift)
18 #define GPIO_IER(gpio) (0x02 << (gpio)->reg_shift)
19 #define GPIO_ISR(gpio) (0x03 << (gpio)->reg_shift)
20 #define GPIO_PTR(gpio) (0x04 << (gpio)->reg_shift)
42 err = i2c_smbus_read_byte_data(adnp->client, offset); in adnp_read()
44 dev_err(adnp->gpio.parent, "%s failed: %d\n", in adnp_read()
57 err = i2c_smbus_write_byte_data(adnp->client, offset, value); in adnp_write()
[all …]
|
| /linux/arch/mips/sgi-ip32/ |
| H A D | ip32-irq.c | 31 #include "ip32-common.h"
36 crime->control; in flush_crime_bus()
41 mace->perif.ctrl.misc; in flush_mace_bus()
47 * IP0 -> software (ignored)
48 * IP1 -> software (ignored)
49 * IP2 -> (irq0) C crime 1.1 all interrupts; crime 1.5 ???
50 * IP3 -> (irq1) X unknown
51 * IP4 -> (irq2) X unknown
52 * IP5 -> (irq3) X unknown
53 * IP6 -> (irq4) X unknown
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/grandridge/ |
| H A D | uncore-memory.json | 97 "BriefDescription": "CAS count for SubChannel 0 auto-precharge writes",
162 "BriefDescription": "CAS count for SubChannel 1 auto-precharge writes",
236 "BriefDescription": "# of cycles MR4 MRRs was triggered/running",
247 "BriefDescription": "# of cycles MR4 MRRs was triggered/running",
258 "BriefDescription": "# of cycles MR4 MRRs was triggered/running",
269 "BriefDescription": "# of cycles MR4 MRRs was triggered/running",
286 "PublicDescription": "-",
297 "PublicDescription": "-",
308 "PublicDescription": "-",
319 "PublicDescription": "-",
[all...] |
| /linux/drivers/iio/adc/ |
| H A D | envelope-detector.c | 1 // SPDX-License-Identifier: GPL-2.0
11 * The DAC is used to find the peak level of an alternating voltage input
16 * input +------>-------|+ \
18 * .-------. | }---.
20 * | dac|-->--|- / |
24 * | irq|------<-------'
26 * '-------'
62 int level; member
71 * (one-bit memory) for if the interrupt has triggered since last calling
74 * need to service a possible interrupt flood from the comparator when no-one
[all …]
|