Lines Matching +full:level +full:- +full:triggered

1 * ARC-HS Interrupt Distribution Unit
3   This optional 2nd level interrupt controller can be used in SMP configurations
9 - compatible: "snps,archs-idu-intc"
10 - interrupt-controller: This is an interrupt controller.
11 - #interrupt-cells: Must be <1> or <2>.
18     - bits[3:0] trigger type and level flags
19         1 = low-to-high edge triggered
20         2 = NOT SUPPORTED (high-to-low edge triggered)
21         4 = active high level-sensitive <<< DEFAULT
22         8 = NOT SUPPORTED (active low level-sensitive)
23   When no second cell is specified, the interrupt is assumed to be level
30 	core_intc: core-interrupt-controller {
31 		compatible = "snps,archs-intc";
32 		interrupt-controller;
33 		#interrupt-cells = <1>;
36 	idu_intc: idu-interrupt-controller {
37 		compatible = "snps,archs-idu-intc";
38 		interrupt-controller;
39 		interrupt-parent = <&core_intc>;
40 		#interrupt-cells = <1>;
44 		interrupt-parent = <&idu_intc>;