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/linux/Documentation/devicetree/bindings/display/
H A Dxylon,logicvc-display.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/display/xylon,logicvc-display.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Paul Kocialkowski <paul.kocialkowski@bootlin.com>
16 with Xilinx Zynq-7000 SoCs and Xilinx FPGAs.
20 synthesis time. As a result, many of the device-tree bindings are meant to
24 Layers are declared in the "layers" sub-node and have dedicated configuration.
25 In version 3 of the controller, each layer has fixed memory offset and address
26 starting from the video memory base address for its framebuffer. In version 4,
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/linux/drivers/gpu/drm/atmel-hlcdc/
H A Datmel_hlcdc_plane.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Author: Boris BREZILLON <boris.brezillon@free-electrons.com>
10 #include <linux/mfd/atmel-hlcdc.h>
24 * struct atmel_hlcdc_plane_state - Atmel HLCDC Plane state structure.
26 * @base: DRM plane state
48 struct drm_plane_state base;
79 return container_of(s, struct atmel_hlcdc_plane_state, base); in drm_plane_state_to_atmel_hlcdc_plane_state()
47 struct drm_plane_state base; global() member
749 unsigned int offset = 0; atmel_hlcdc_plane_atomic_check() local
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H A Datmel_hlcdc_dc.h1 /* SPDX-License-Identifier: GPL-2.0-only */
7 * Author: Jean-Jacques Hiblot <jjhiblot@traphandler.com>
8 * Author: Boris BREZILLON <boris.brezillon@free-electrons.com>
95 #define ATMEL_HLCDC_LAYER_SIZE(w, h) (((w) - 1) | (((h) - 1) << 16))
116 #define ATMEL_HLCDC_LAYER_DISC_SIZE(w, h) (((w) - 1) | (((h) -
321 struct drm_plane base; global() member
322 struct atmel_hlcdc_layer layer; global() member
332 atmel_hlcdc_layer_to_plane(struct atmel_hlcdc_layer * layer) atmel_hlcdc_layer_to_plane() argument
435 atmel_hlcdc_layer_write_reg(struct atmel_hlcdc_layer * layer,unsigned int reg,u32 val) atmel_hlcdc_layer_write_reg() argument
441 atmel_hlcdc_layer_read_reg(struct atmel_hlcdc_layer * layer,unsigned int reg) atmel_hlcdc_layer_read_reg() argument
451 atmel_hlcdc_layer_write_cfg(struct atmel_hlcdc_layer * layer,unsigned int cfgid,u32 val) atmel_hlcdc_layer_write_cfg() argument
459 atmel_hlcdc_layer_read_cfg(struct atmel_hlcdc_layer * layer,unsigned int cfgid) atmel_hlcdc_layer_read_cfg() argument
467 atmel_hlcdc_layer_write_clut(struct atmel_hlcdc_layer * layer,unsigned int c,u32 val) atmel_hlcdc_layer_write_clut() argument
475 atmel_hlcdc_layer_init(struct atmel_hlcdc_layer * layer,const struct atmel_hlcdc_layer_desc * desc,struct regmap * regmap) atmel_hlcdc_layer_init() argument
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/linux/drivers/gpu/drm/msm/disp/dpu1/
H A Ddpu_hw_catalog.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
4 * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved.
32 * SSPP sub-blocks/features
34 …* @DPU_SSPP_SCALER_QSEED3_COMPATIBLE, QSEED3-compatible alogorithm support (includes QSEED3, QSEE…
37 * @DPU_SSPP_CSC_10BIT, Support of 10-bit Color space conversion
38 * @DPU_SSPP_CURSOR, SSPP can be used as a cursor layer
68 * MIXER sub-blocks/features
69 * @DPU_MIXER_SOURCESPLIT Layer mixer supports source-split configuration
78 * DSPP sub-blocks
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/linux/drivers/gpu/drm/arm/
H A Dmalidp_hw.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * (C) COPYRIGHT 2013-2016 ARM Limited. All rights reserved.
25 /* Mali DP layer IDs */
43 u8 layer; /* bitmask of layers supporting it */ member
52 * base register offsets
62 u16 id; /* layer ID */
63 u16 base; /* address offset for the register bank */ member
64 u16 ptr; /* address offset for the pointer register */
65 u16 stride_offset; /* offset to the first stride register. */
66 s16 yuv2rgb_offset; /* offset to the YUV->RGB matrix entries */
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/linux/drivers/gpu/drm/logicvc/
H A Dlogicvc_layer.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2019-2022 Bootlin
86 struct drm_device *drm_dev = drm_plane->dev; in logicvc_plane_atomic_check()
87 struct logicvc_layer *layer = logicvc_layer(drm_plane); in logicvc_plane_atomic_check() local
96 if (!new_state->crtc) in logicvc_plane_atomic_check()
99 crtc_state = drm_atomic_get_new_crtc_state(new_state->state, in logicvc_plane_atomic_check()
100 new_state->crtc); in logicvc_plane_atomic_check()
102 return -EINVA in logicvc_plane_atomic_check()
140 struct logicvc_layer *layer = logicvc_layer(drm_plane); logicvc_plane_atomic_update() local
237 struct logicvc_layer *layer = logicvc_layer(drm_plane); logicvc_plane_atomic_disable() local
260 logicvc_layer_buffer_find_setup(struct logicvc_drm * logicvc,struct logicvc_layer * layer,struct drm_plane_state * state,struct logicvc_layer_buffer_setup * setup) logicvc_layer_buffer_find_setup() argument
353 logicvc_layer_formats_lookup(struct logicvc_layer * layer) logicvc_layer_formats_lookup() argument
383 logicvc_layer_config_parse(struct logicvc_drm * logicvc,struct logicvc_layer * layer) logicvc_layer_config_parse() argument
435 struct logicvc_layer *layer; logicvc_layer_get_from_index() local
447 struct logicvc_layer *layer; logicvc_layer_get_from_type() local
466 struct logicvc_layer *layer = NULL; logicvc_layer_init() local
558 logicvc_layer_fini(struct logicvc_drm * logicvc,struct logicvc_layer * layer) logicvc_layer_fini() argument
569 struct logicvc_layer *layer; logicvc_layers_attach_crtc() local
586 struct logicvc_layer *layer; logicvc_layers_init() local
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H A Dlogicvc_of.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2019-2022 Bootlin
14 { "lvds-4bits", LOGICVC_DISPLAY_INTERFACE_LVDS_4BITS },
15 { "lvds-3bits", LOGICVC_DISPLAY_INTERFACE_LVDS_3BITS },
33 { "layer", LOGICVC_LAYER_ALPHA_LAYER },
40 .name = "xylon,display-interface",
48 .name = "xylon,display-colorspace",
56 .name = "xylon,display-depth",
60 .name = "xylon,row-stride",
67 .name = "xylon,background-layer",
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/linux/drivers/gpu/drm/sprd/
H A Dsprd_dpu.h1 /* SPDX-License-Identifier: GPL-2.0 */
23 /* DPU Layer registers offset */
35 * @base: DPU controller base address
46 void __iomem *base; member
64 struct drm_crtc base; member
71 return container_of(crtc, struct sprd_dpu, base); in to_sprd_crtc()
75 dpu_reg_set(struct dpu_context *ctx, u32 offset, u32 set_bits) in dpu_reg_set() argument
77 u32 bits = readl_relaxed(ctx->base + offset); in dpu_reg_set()
79 writel(bits | set_bits, ctx->base + offset); in dpu_reg_set()
83 dpu_reg_clr(struct dpu_context *ctx, u32 offset, u32 clr_bits) in dpu_reg_clr() argument
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/linux/drivers/gpu/drm/vmwgfx/
H A Dvmw_surface_cache.h1 /* SPDX-License-Identifier: GPL-2.0 OR MIT */
4 * Copyright (c) 2021-2024 Broadcom. All Rights Reserved. The term
43 return (tmp > (uint64_t) ((u32) -1)) ? (u32) -1 : tmp; in clamped_umul32()
47 * vmw_surface_get_desc - Look up the appropriate SVGA3dSurfaceDesc for the
60 * vmw_surface_get_mip_size - Given a base level size and the mip level,
80 block_size->width = __KERNEL_DIV_ROUND_UP(pixel_size->width, in vmw_surface_get_size_in_blocks()
81 desc->blockSize.width); in vmw_surface_get_size_in_blocks()
82 block_size->height = __KERNEL_DIV_ROUND_UP(pixel_size->height, in vmw_surface_get_size_in_blocks()
83 desc->blockSize.height); in vmw_surface_get_size_in_blocks()
84 block_size->depth = __KERNEL_DIV_ROUND_UP(pixel_size->depth, in vmw_surface_get_size_in_blocks()
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/linux/drivers/usb/mtu3/
H A Dmtu3.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * mtu3.h - MediaTek USB3 DRD header
35 #define MU3D_EP_TXCR0(epnum) (U3D_TX1CSR0 + (((epnum) - 1) * 0x10))
36 #define MU3D_EP_TXCR1(epnum) (U3D_TX1CSR1 + (((epnum) - 1) * 0x10))
37 #define MU3D_EP_TXCR2(epnum) (U3D_TX1CSR2 + (((epnum) - 1) * 0x10))
39 #define MU3D_EP_RXCR0(epnum) (U3D_RX1CSR0 + (((epnum) - 1) * 0x10))
40 #define MU3D_EP_RXCR1(epnum) (U3D_RX1CSR1 + (((epnum) - 1) * 0x10))
41 #define MU3D_EP_RXCR2(epnum) (U3D_RX1CSR2 + (((epnum) - 1) * 0x10))
43 #define USB_QMU_TQHIAR(epnum) (U3D_TXQHIAR1 + (((epnum) - 1) * 0x4))
44 #define USB_QMU_RQHIAR(epnum) (U3D_RXQHIAR1 + (((epnum) - 1) * 0x4))
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/linux/drivers/gpu/drm/rockchip/
H A Drockchip_vop2_reg.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Author: Andy Yan <andy.yan@rock-chips.com>
69 DRM_FORMAT_YUV420_8BIT, /* yuv420_8bit non-Linear mode only */
70 DRM_FORMAT_YUV420_10BIT, /* yuv420_10bit non-Linear mode only */
71 DRM_FORMAT_YUYV, /* yuv422_8bit non-Linear mode only*/
72 DRM_FORMAT_Y210, /* yuv422_10bit non-Linear mode only */
79 * rfbc is a rockchip defined non-linear mode, produced by
563 .offset = 0xc00,
569 .offset = 0xd00,
575 .offset = 0xe00,
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/linux/Documentation/devicetree/bindings/display/mediatek/
H A Dmediatek,padding.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chun-Kuang Hu <chunkuang.hu@kernel.org>
11 - Philipp Zabel <p.zabel@pengutronix.de>
14 Padding provides ability to add pixels to width and height of a layer with
16 width of a layer to be 2-pixel-align, or 4-pixel-align when ETHDR is enabled,
24 - enum:
25 - mediatek,mt8188-disp-padding
26 - mediatek,mt8195-mdp3-padding
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/linux/drivers/gpu/drm/arm/display/komeda/
H A Dkomeda_framebuffer.c1 // SPDX-License-Identifier: GPL-2.0
22 for (i = 0; i < fb->format->num_planes; i++) in komeda_fb_destroy()
23 drm_gem_object_put(fb->obj[i]); in komeda_fb_destroy()
32 return drm_gem_handle_create(file, fb->obj[0], handle); in komeda_fb_create_handle()
44 struct drm_framebuffer *fb = &kfb->base; in komeda_fb_afbc_size_check()
45 const struct drm_format_info *info = fb->forma in komeda_fb_afbc_size_check()
244 u32 offset, plane_x, plane_y, block_w, block_sz; komeda_fb_get_pixel_addr() local
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/linux/Documentation/devicetree/bindings/media/
H A Dti,cal.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Texas Instruments DRA72x CAMERA ADAPTATION LAYER (CAL)
10 - Benoit Parrot <bparrot@ti.com>
12 description: |-
13 The Camera Adaptation Layer (CAL) is a key component for image capture
15 processing capability to connect CSI2 image-sensor modules to the
24 - ti,dra72-cal
26 - ti,dra72-pre-es2-cal
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/linux/include/misc/
H A Docxl.h1 // SPDX-License-Identifier: GPL-2.0+
14 * reuse common code. A bit like a in-kernel library.
22 int dvsec_afu_control_pos; /* offset of AFU control DVSEC */
32 u8 pp_mmio_bar; /* per-process MMIO area */
44 int dvsec_tl_pos; /* offset of the Transaction Layer DVSEC */
45 int dvsec_function_pos; /* offset of the Function DVSEC */
46 int dvsec_afu_info_pos; /* offset of the AFU information DVSEC */
52 OCXL_BIG_ENDIAN = 0, /**< AFU data is big-endian */
53 OCXL_LITTLE_ENDIAN = 1, /**< AFU data is little-endian */
65 * ocxl_function_open() - Open an OpenCAPI function on an OpenCAPI device
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/linux/drivers/irqchip/
H A Dspear-shirq.c2 * SPEAr platform shared irq layer source file
4 * Copyright (C) 2009-2012 ST Microelectronics
31 * base: Base register address
32 * status_reg: Status register offset for chained interrupt handler
33 * mask_reg: Mask register offset for irq chip
35 * virq_base: Base virtual interrupt number
37 * offset: Bit offset of the first interrupt
42 void __iomem *base; member
48 u32 offset; member
61 u32 val, shift = d->irq - shirq->virq_base + shirq->offset; in shirq_irq_mask()
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/linux/drivers/net/ethernet/chelsio/cxgb3/
H A Dcxgb3_ctl_defs.h2 * Copyright (c) 2003-2008 Chelsio, Inc. All rights reserved.
14 * - Redistributions of source code must retain the above
18 * - Redistributions in binary form must reproduce the above
66 * Structure used to describe a TID range. Valid TIDs are [base, base+num).
69 unsigned int base; /* first TID */ member
116 * Structure used to return information to the iscsi layer.
119 unsigned int offset; member
130 * Structure used to return information to the RDMA layer.
133 unsigned int tpt_base; /* TPT base address */
135 unsigned int pbl_base; /* PBL base address */
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/linux/include/linux/
H A Dedac.h6 * 2006-2008 (c) MontaVista Software, Inc. This file is licensed under
26 #define EDAC_OPSTATE_INVAL -1
60 * enum dev_type - describe the type of memory DRAM chips used at the stick
93 * enum hw_event_mc_err_type - type of the detected error
95 * @HW_EVENT_ERR_CORRECTED: Corrected Error - Indicates that an ECC
97 * @HW_EVENT_ERR_UNCORRECTED: Uncorrected Error - Indicates an error that
101 * it for example, by re-trying the operation).
102 * @HW_EVENT_ERR_DEFERRED: Deferred Error - Indicates an uncorrectable
108 * @HW_EVENT_ERR_FATAL: Fatal Error - Uncorrected error that could not
110 * @HW_EVENT_ERR_INFO: Informational - The CPER spec defines a forth
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/linux/drivers/edac/
H A Darmada_xp_edac.c1 // SPDX-License-Identifier: GPL-2.0
12 #include <asm/hardware/cache-l2x0.h>
13 #include <asm/hardware/cache-aurora-l2.h>
74 void __iomem *base; member
88 if (drvdata->width == 8) { in axp_mc_calc_address()
90 if (drvdata->cs_addr_sel[cs]) in axp_mc_calc_address()
100 } else if (drvdata->width == 4) { in axp_mc_calc_address()
102 if (drvdata->cs_addr_sel[cs]) in axp_mc_calc_address()
114 if (drvdata->cs_addr_sel[cs]) in axp_mc_calc_address()
129 struct axp_mc_drvdata *drvdata = mci->pvt_info; in axp_mc_check()
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/linux/include/linux/surface_aggregator/
H A Dserial_hub.h1 /* SPDX-License-Identifier: GPL-2.0+ */
5 * Lower-level communication layers and SSH protocol definitions for the
7 * packet- and request-based communication with the SSAM EC via SSH.
9 * Copyright (C) 2019-2021 Maximilian Luz <luzmaximilian@gmail.com>
15 #include <linux/crc-itu-t.h>
22 /* -- Data structures for SAM-over-SSH communication. ----------------------- */
25 * enum ssh_frame_type - Frame types for SSH frames.
42 * For command-type payloads, this can also mean that the command is
53 * struct ssh_frame - SSH communication frame.
68 * SSH_FRAME_MAX_PAYLOAD_SIZE - Maximum SSH frame payload length in bytes.
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/linux/drivers/rtc/
H A Drtc-meson.c1 // SPDX-License-Identifier: GPL-2.0
19 #include <linux/nvmem-provider.h>
46 /* rtc registers accessed via rtc-serial interface */
70 .name = "peripheral-registers",
77 /* RTC front-end serialiser controls */
82 regmap_update_bits(rtc->peripheral, RTC_ADDR0, RTC_ADDR0_LINE_SCLK, 0); in meson_rtc_sclk_pulse()
84 regmap_update_bits(rtc->peripheral, RTC_ADDR0, RTC_ADDR0_LINE_SCLK, in meson_rtc_sclk_pulse()
90 regmap_update_bits(rtc->peripheral, RTC_ADDR0, RTC_ADDR0_LINE_SDI, in meson_rtc_send_bit()
98 u32 bit = 1 << (nr - 1); in meson_rtc_send_bits()
108 regmap_update_bits(rtc->peripheral, RTC_ADDR0, RTC_ADDR0_LINE_SEN, 0); in meson_rtc_set_dir()
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/linux/Documentation/trace/
H A Dkprobetrace.rst2 Kprobe-based Event Tracing
8 --------
9 These events are similar to tracepoint-based events. Instead of tracepoints,
13 Unlike the tracepoint-based event, this can be added and removed
28 -------------------------
34 -:[GRP/][EVENT] : Clear a probe
40 SYM[+offs] : Symbol+offset where the probe is inserted.
50 @SYM[+|-offs] : Fetch memory at SYM +|- offs (SYM should be a data symbol)
56 +|-[u]OFFS(FETCHARG) : Fetch memory at FETCHARG +|- OFFS address.(\*3)(\*4)
61 (x8/x16/x32/x64), VFS layer common type(%pd/%pD), "char",
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/linux/drivers/cdrom/
H A Dcdrom.c9 Uniform CD-ROM driver for Linux.
10 See Documentation/cdrom/cdrom-standard.rst for usage information.
13 software that uses CD-ROMs and the various low-level drivers that
15 Patches that work are more welcome though. ;-)
18 ----------------------------------
19 1.00 Date Unknown -- David van Leeuwen <david@tm.tno.nl>
20 -- Initial version by David A. van Leeuwen. I don't have a detailed
23 2.00 Dec 2, 1997 -- Erik Andersen <andersee@debian.org>
24 -- New maintainer! As David A. van Leeuwen has been too busy to actively
28 -- Added (rudimentary) sysctl interface. I realize this is really weak
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/linux/drivers/net/ethernet/dec/tulip/
H A Duli526x.c1 // SPDX-License-Identifier: GPL-2.0-or-later
27 #include <linux/dma-mapping.h>
38 /* Board/System/Debug information/definition ---------------- */
45 #define TX_FREE_DESC_CNT (TX_DESC_CNT - 2) /* Max TX packet count */
46 #define TX_WAKE_DESC_CNT (TX_DESC_CNT - 3) /* TX wakeup count */
75 #define ULI526X_TX_TIMEOUT ((16*HZ)/2) /* tx packet time-out time 8 s" */
76 #define ULI526X_TX_KICK (4*HZ/2) /* tx packet Kick-out time 2 s" */
105 /* Structure/enum declaration ------------------------------- */
127 void __iomem *ioaddr; /* I/O base address */
196 /* Global variable declaration ----------------------------- */
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/linux/drivers/gpu/drm/arm/display/komeda/d71/
H A Dd71_component.c1 // SPDX-License-Identifier: GPL-2.0
65 for (i = 0; i < PIPELINE_INFO_N_VALID_INPUTS(blk->pipeline_info); i++) { in get_valid_inputs()
66 get_resources_id(blk->input_ids[i], NULL, &comp_id); in get_valid_inputs()
75 static void get_values_from_reg(void __iomem *reg, u32 offset, in get_values_from_reg() argument
81 addr = offset + (i << 2); in get_values_from_reg()
117 if (!d71->periph_addr) in __get_blk_line_size()
125 return __get_blk_line_size(d71, reg, d71->max_line_size); in get_blk_line_size()
178 struct komeda_component_output *input = &st->inputs[idx]; in to_d71_input_id()
181 if (has_bit(idx, st->active_inputs)) in to_d71_input_id()
182 return input->component->hw_id + input->output_port; in to_d71_input_id()
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