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/linux/tools/testing/selftests/drivers/net/mlxsw/
H A Dethtool_lanes.sh28 busywait $TIMEOUT sh -c "ethtool $swp1 | grep -q Lanes:"
30 log_test "SKIP: driver does not support lanes setting"
41 local lanes=$1; shift
45 chosen_lanes=$(ethtool $dev | grep 'Lanes:')
46 chosen_lanes=${chosen_lanes#*"Lanes: "}
48 ((chosen_lanes == lanes))
49 check_err $? "swp1 advertise $max_speed and $lanes, devs sync to $chosen_lanes"
66 ethtool -s $swp1 speed $max_speed lanes $unsupported_lanes $autoneg_str &> /dev/null
67 check_fail $? "Unsuccessful $unsupported_lanes lanes setting was expected"
94 local lanes=$1; shift
[all …]
/linux/tools/testing/selftests/drivers/net/hw/
H A Ddevlink_port_split.py12 # Test port split configuration using devlink-port lanes attribute.
77 Get the $port's maximum number of lanes.
78 Return: number of lanes, e.g. 1, 2, 4 and 8.
86 if 'lanes' in values:
87 lanes = values['lanes']
89 lanes = 0
90 return lanes
150 def exists_and_lanes(ports, lanes, dev): argument
153 $lanes number of lanes after splitting.
162 if max_lanes != lanes:
[all …]
/linux/drivers/gpu/drm/hisilicon/hibmc/dp/
H A Ddp_link.c35 dp->link.cap.lanes == 0x2 ? 0x3 : 0x1); in hibmc_dp_link_training_configure()
37 dp->link.cap.lanes == 0x2 ? 0x1 : 0); in hibmc_dp_link_training_configure()
44 buf[1] = DP_LANE_COUNT_ENHANCED_FRAME_EN | dp->link.cap.lanes; in hibmc_dp_link_training_configure()
47 drm_dbg_dp(dp->dev, "dp aux write link rate and lanes failed, ret: %d\n", ret); in hibmc_dp_link_training_configure()
122 for (i = 0; i < dp->link.cap.lanes; i++) in hibmc_dp_link_training_cr_pre()
129 ret = drm_dp_dpcd_write(dp->aux, DP_TRAINING_LANE0_SET, train_set, dp->link.cap.lanes); in hibmc_dp_link_training_cr_pre()
130 if (ret != dp->link.cap.lanes) { in hibmc_dp_link_training_cr_pre()
144 for (lane = 0; lane < dp->link.cap.lanes; lane++) in hibmc_dp_link_get_adjust_train()
183 switch (dp->link.cap.lanes) { in hibmc_dp_link_reduce_lane()
185 dp->link.cap.lanes--; in hibmc_dp_link_reduce_lane()
[all …]
/linux/arch/arm64/boot/dts/ti/
H A Dk3-j722s-evm-csi2-quad-tevi-ov5640.dtso111 clock-lanes = <0>;
112 data-lanes = <1 2>;
142 clock-lanes = <0>;
143 data-lanes = <1 2>;
178 clock-lanes = <0>;
179 data-lanes = <1 2>;
209 clock-lanes = <0>;
210 data-lanes = <1 2>;
229 clock-lanes = <0>;
230 data-lanes = <1 2>;
[all …]
H A Dk3-j722s-evm-csi2-quad-rpi-cam-imx219.dtso114 clock-lanes = <0>;
115 data-lanes = <1 2>;
146 clock-lanes = <0>;
147 data-lanes = <1 2>;
183 clock-lanes = <0>;
184 data-lanes = <1 2>;
215 clock-lanes = <0>;
216 data-lanes = <1 2>;
235 clock-lanes = <0>;
236 data-lanes = <1 2>;
[all …]
H A Dk3-j721e-sk-csi2-dual-imx219.dtso72 clock-lanes = <0>;
73 data-lanes = <1 2>;
96 clock-lanes = <0>;
97 data-lanes = <1 2>;
116 clock-lanes = <0>;
117 data-lanes = <1 2>;
163 clock-lanes = <0>;
164 data-lanes = <1 2>;
/linux/arch/arm64/boot/dts/renesas/
H A Dr8a779a0-falcon-csi-dsi.dtsi21 clock-lanes = <0>;
22 data-lanes = <1 2 3 4>;
40 clock-lanes = <0>;
41 data-lanes = <1 2 3 4>;
59 clock-lanes = <0>;
60 data-lanes = <1 2 3 4>;
111 clock-lanes = <0>;
112 data-lanes = <1 2 3 4>;
132 clock-lanes = <0>;
133 data-lanes = <1 2 3 4>;
[all …]
H A Dhihope-rzg2-ex-aistarvision-mipi-adapter-2.1.dtsi18 clock-lanes = <0>;
19 data-lanes = <1 2>;
32 clock-lanes = <0>;
33 data-lanes = <1 2>;
49 clock-lanes = <0>;
50 data-lanes = <1 2>;
63 clock-lanes = <0>;
64 data-lanes = <1 2>;
H A Dwhite-hawk-csi-dsi.dtsi22 clock-lanes = <0>;
23 data-lanes = <1 2 3>;
45 clock-lanes = <0>;
46 data-lanes = <1 2 3>;
93 clock-lanes = <0>;
94 data-lanes = <1 2 3>;
114 clock-lanes = <0>;
115 data-lanes = <1 2 3>;
H A Dr8a774c0-ek874-mipi-2.1.dts38 clock-lanes = <0>;
39 data-lanes = <1 2>;
52 clock-lanes = <0>;
53 data-lanes = <1 2>;
62 clock-lanes = <0>;
63 data-lanes = <1 2>;
/linux/drivers/net/ethernet/mellanox/mlx5/core/
H A Dport.c1062 [MLX5E_1000BASE_CX_SGMII] = {.speed = 1000, .lanes = 1},
1063 [MLX5E_1000BASE_KX] = {.speed = 1000, .lanes = 1},
1064 [MLX5E_10GBASE_CX4] = {.speed = 10000, .lanes = 4},
1065 [MLX5E_10GBASE_KX4] = {.speed = 10000, .lanes = 4},
1066 [MLX5E_10GBASE_KR] = {.speed = 10000, .lanes = 1},
1067 [MLX5E_20GBASE_KR2] = {.speed = 20000, .lanes = 2},
1068 [MLX5E_40GBASE_CR4] = {.speed = 40000, .lanes = 4},
1069 [MLX5E_40GBASE_KR4] = {.speed = 40000, .lanes = 4},
1070 [MLX5E_56GBASE_R4] = {.speed = 56000, .lanes = 4},
1071 [MLX5E_10GBASE_CR] = {.speed = 10000, .lanes = 1},
[all …]
/linux/drivers/media/platform/ti/omap3isp/
H A Dispcsiphy.c167 struct isp_csiphy_lanes_cfg *lanes; in omap3isp_csiphy_config() local
179 lanes = &buscfg->bus.ccp2.lanecfg; in omap3isp_csiphy_config()
182 lanes = &buscfg->bus.csi2.lanecfg; in omap3isp_csiphy_config()
189 /* Clock and data lanes verification */ in omap3isp_csiphy_config()
191 if (lanes->data[i].pol > 1 || lanes->data[i].pos > 3) in omap3isp_csiphy_config()
194 if (used_lanes & (1 << lanes->data[i].pos)) in omap3isp_csiphy_config()
197 used_lanes |= 1 << lanes->data[i].pos; in omap3isp_csiphy_config()
200 if (lanes->clk.pol > 1 || lanes->clk.pos > 3) in omap3isp_csiphy_config()
203 if (lanes->clk.pos == 0 || used_lanes & (1 << lanes->clk.pos)) in omap3isp_csiphy_config()
215 /* CSI-2 is DDR and we only count used lanes. */ in omap3isp_csiphy_config()
[all …]
/linux/Documentation/devicetree/bindings/media/
H A Dbrcm,bcm2835-unicam.yaml55 brcm,num-data-lanes:
59 Number of CSI-2 data lanes supported by this Unicam instance. The number
60 of data lanes actively used is specified with the data-lanes endpoint
77 data-lanes: true
82 - data-lanes
96 - brcm,num-data-lanes
118 brcm,num-data-lanes = <2>;
123 data-lanes = <1 2>;
H A Dti,cal.yaml86 clock-lanes:
89 data-lanes:
104 clock-lanes:
107 data-lanes:
146 clock-lanes = <0>;
147 data-lanes = <1 2>;
170 clock-lanes = <0>;
171 data-lanes = <1 2>;
/linux/net/ethtool/
H A Dlinkmodes.c49 data->ksettings.lanes = 0; in linkmodes_prepare_data()
133 if (ksettings->lanes && in linkmodes_fill_reply()
134 nla_put_u32(skb, ETHTOOL_A_LINKMODES_LANES, ksettings->lanes)) in linkmodes_fill_reply()
168 * lanes and duplex values. Called when autonegotiation is on, speed, lanes or
190 (!req_lanes || info->lanes == ksettings->lanes) && in ethnl_auto_linkmodes()
229 "lanes value is invalid"); in ethnl_check_linkmodes()
264 /* If autoneg is off and lanes parameter is not supported by the in ethnl_update_linkmodes()
270 "lanes configuration not supported by device"); in ethnl_update_linkmodes()
273 } else if (!lsettings->autoneg && ksettings->lanes) { in ethnl_update_linkmodes()
274 /* If autoneg is off and lanes parameter is not passed from user but in ethnl_update_linkmodes()
[all …]
/linux/Documentation/devicetree/bindings/pci/
H A Dnvidia,tegra20-pcie.txt104 - If lanes 0 to 3 are used:
107 - If lanes 4 or 5 are used:
148 - nvidia,num-lanes: Number of lanes to use for this port. Valid combinations
150 - Root port 0 uses 4 lanes, root port 1 is unused.
151 - Both root ports use 2 lanes.
157 number of lanes in the nvidia,num-lanes property. Entries are of the form
158 "pcie-N": where N ranges from 0 to the value specified in nvidia,num-lanes.
210 nvidia,num-lanes = <2>;
224 nvidia,num-lanes = <2>;
316 nvidia,num-lanes = <2>;
[all …]
/linux/Documentation/devicetree/bindings/media/xilinx/
H A Dxlnx,csi2rxss.yaml88 xlnx,en-active-lanes:
91 Present if the number of active lanes can be re-configured at
92 runtime in the Protocol Configuration Register. Otherwise all lanes,
115 data-lanes:
121 1 2 - For 2 lanes enabled in IP.
122 1 2 3 - For 3 lanes enabled in IP.
123 1 2 3 4 - For 4 lanes enabled in IP.
131 - data-lanes
180 xlnx,en-active-lanes;
195 data-lanes = <1 2 3 4>;
/linux/include/linux/phy/
H A Dphy-dp.h31 * @lanes:
33 * Number of active, consecutive, data lanes, starting from
38 unsigned int lanes; member
44 * to be used by particular lanes. One value per lane.
55 * used by particular lanes. One value per lane.
91 * and pre-emphasis to requested values. Only lanes specified
92 * by "lanes" parameter will be affected.
/linux/drivers/video/fbdev/omap2/omapfb/dss/
H A Dhdmi_common.c18 prop = of_find_property(ep, "lanes", &len); in hdmi_parse_lanes_of()
20 u32 lanes[8]; in hdmi_parse_lanes_of() local
22 if (len / sizeof(u32) != ARRAY_SIZE(lanes)) { in hdmi_parse_lanes_of()
23 dev_err(&pdev->dev, "bad number of lanes\n"); in hdmi_parse_lanes_of()
27 r = of_property_read_u32_array(ep, "lanes", lanes, in hdmi_parse_lanes_of()
28 ARRAY_SIZE(lanes)); in hdmi_parse_lanes_of()
34 r = hdmi_phy_parse_lanes(phy, lanes); in hdmi_parse_lanes_of()
/linux/drivers/gpu/drm/omapdrm/dss/
H A Dhdmi_common.c18 prop = of_find_property(ep, "lanes", &len); in hdmi_parse_lanes_of()
20 u32 lanes[8]; in hdmi_parse_lanes_of() local
22 if (len / sizeof(u32) != ARRAY_SIZE(lanes)) { in hdmi_parse_lanes_of()
23 dev_err(&pdev->dev, "bad number of lanes\n"); in hdmi_parse_lanes_of()
27 r = of_property_read_u32_array(ep, "lanes", lanes, in hdmi_parse_lanes_of()
28 ARRAY_SIZE(lanes)); in hdmi_parse_lanes_of()
34 r = hdmi_phy_parse_lanes(phy, lanes); in hdmi_parse_lanes_of()
/linux/Documentation/devicetree/bindings/phy/
H A Dnvidia,tegra124-xusb-padctl.yaml14 The Tegra XUSB pad controller manages a set of I/O lanes (with differential
17 documentation. Each such "pad" may control either one or multiple lanes,
18 and thus contains any logic common to all its lanes. Each lane can be
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
25 ports (e.g. PCIe) and the lanes.
88 order to use the pad and any of its lanes, this property must be set
105 lanes:
149 lanes:
177 lanes:
[all …]
H A Dphy-cadence-torrent.yaml80 Each group of PHY lanes with a single master lane should be represented as a sub-node.
92 Contains list of resets, one per lane, to get all the link lanes out of reset.
99 Specifies the type of PHY for which the group of PHY lanes is used.
104 cdns,num-lanes:
106 Number of lanes.
132 - cdns,num-lanes
174 cdns,num-lanes = <4>;
202 cdns,num-lanes = <2>;
211 cdns,num-lanes = <1>;
/linux/drivers/net/ethernet/netronome/nfp/
H A Dnfp_devlink.c39 nfp_devlink_set_lanes(struct nfp_pf *pf, unsigned int idx, unsigned int lanes) in nfp_devlink_set_lanes() argument
48 ret = __nfp_eth_set_split(nsp, lanes); in nfp_devlink_set_lanes()
69 unsigned int lanes; in nfp_devlink_port_split() local
84 lanes = eth_port.port_lanes / count; in nfp_devlink_port_split()
85 if (eth_port.lanes == 10 && count == 2) in nfp_devlink_port_split()
86 lanes = 8 / count; in nfp_devlink_port_split()
88 return nfp_devlink_set_lanes(pf, eth_port.index, lanes); in nfp_devlink_port_split()
97 unsigned int lanes; in nfp_devlink_port_unsplit() local
112 lanes = eth_port.port_lanes; in nfp_devlink_port_unsplit()
114 lanes = 10; in nfp_devlink_port_unsplit()
[all …]
/linux/arch/arm64/boot/dts/nvidia/
H A Dtegra234-p3768-0000+p3767.dtsi65 lanes {
84 lanes {
138 phys = <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-0}>,
139 <&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-1}>;
146 phys = <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-0}>,
147 <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-1}>,
148 <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-2}>,
149 <&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-0}>,
150 <&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-1}>;
159 num-lanes = <2>;
/linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dpppcielanes.c33 /* For converting from number of lanes to lane bits. */
37 2, /* 2 Lanes */
39 3, /* 4 Lanes */
43 4, /* 8 Lanes */
47 5, /* 12 Lanes (Not actually supported) */
51 6 /* 16 Lanes */

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