1*f767eb91SVaishnav Achath// SPDX-License-Identifier: GPL-2.0-only OR MIT 2*f767eb91SVaishnav Achath/** 3*f767eb91SVaishnav Achath * DT Overlay for dual RPi Camera V2.1 (Sony IMX219) interfaced with CSI2 4*f767eb91SVaishnav Achath * on J721E SK, AM68 SK or AM69-SK board. 5*f767eb91SVaishnav Achath * https://datasheets.raspberrypi.org/camera/camera-v2-schematic.pdf 6*f767eb91SVaishnav Achath * 7*f767eb91SVaishnav Achath * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ 8*f767eb91SVaishnav Achath */ 9*f767eb91SVaishnav Achath 10*f767eb91SVaishnav Achath/dts-v1/; 11*f767eb91SVaishnav Achath/plugin/; 12*f767eb91SVaishnav Achath 13*f767eb91SVaishnav Achath#include <dt-bindings/gpio/gpio.h> 14*f767eb91SVaishnav Achath#include "k3-pinctrl.h" 15*f767eb91SVaishnav Achath 16*f767eb91SVaishnav Achath&{/} { 17*f767eb91SVaishnav Achath clk_imx219_fixed: imx219-xclk { 18*f767eb91SVaishnav Achath compatible = "fixed-clock"; 19*f767eb91SVaishnav Achath #clock-cells = <0>; 20*f767eb91SVaishnav Achath clock-frequency = <24000000>; 21*f767eb91SVaishnav Achath }; 22*f767eb91SVaishnav Achath}; 23*f767eb91SVaishnav Achath 24*f767eb91SVaishnav Achath&csi_mux { 25*f767eb91SVaishnav Achath idle-state = <1>; 26*f767eb91SVaishnav Achath}; 27*f767eb91SVaishnav Achath 28*f767eb91SVaishnav Achath/* CAM0 I2C */ 29*f767eb91SVaishnav Achath&cam0_i2c { 30*f767eb91SVaishnav Achath #address-cells = <1>; 31*f767eb91SVaishnav Achath #size-cells = <0>; 32*f767eb91SVaishnav Achath imx219_0: imx219-0@10 { 33*f767eb91SVaishnav Achath compatible = "sony,imx219"; 34*f767eb91SVaishnav Achath reg = <0x10>; 35*f767eb91SVaishnav Achath 36*f767eb91SVaishnav Achath clocks = <&clk_imx219_fixed>; 37*f767eb91SVaishnav Achath clock-names = "xclk"; 38*f767eb91SVaishnav Achath 39*f767eb91SVaishnav Achath port { 40*f767eb91SVaishnav Achath csi2_cam0: endpoint { 41*f767eb91SVaishnav Achath remote-endpoint = <&csi2rx0_in_sensor>; 42*f767eb91SVaishnav Achath link-frequencies = /bits/ 64 <456000000>; 43*f767eb91SVaishnav Achath clock-lanes = <0>; 44*f767eb91SVaishnav Achath data-lanes = <1 2>; 45*f767eb91SVaishnav Achath }; 46*f767eb91SVaishnav Achath }; 47*f767eb91SVaishnav Achath }; 48*f767eb91SVaishnav Achath}; 49*f767eb91SVaishnav Achath 50*f767eb91SVaishnav Achath/* CAM1 I2C */ 51*f767eb91SVaishnav Achath&cam1_i2c { 52*f767eb91SVaishnav Achath #address-cells = <1>; 53*f767eb91SVaishnav Achath #size-cells = <0>; 54*f767eb91SVaishnav Achath imx219_1: imx219-1@10 { 55*f767eb91SVaishnav Achath compatible = "sony,imx219"; 56*f767eb91SVaishnav Achath reg = <0x10>; 57*f767eb91SVaishnav Achath 58*f767eb91SVaishnav Achath clocks = <&clk_imx219_fixed>; 59*f767eb91SVaishnav Achath clock-names = "xclk"; 60*f767eb91SVaishnav Achath 61*f767eb91SVaishnav Achath port { 62*f767eb91SVaishnav Achath csi2_cam1: endpoint { 63*f767eb91SVaishnav Achath remote-endpoint = <&csi2rx1_in_sensor>; 64*f767eb91SVaishnav Achath link-frequencies = /bits/ 64 <456000000>; 65*f767eb91SVaishnav Achath clock-lanes = <0>; 66*f767eb91SVaishnav Achath data-lanes = <1 2>; 67*f767eb91SVaishnav Achath }; 68*f767eb91SVaishnav Achath }; 69*f767eb91SVaishnav Achath }; 70*f767eb91SVaishnav Achath}; 71*f767eb91SVaishnav Achath 72*f767eb91SVaishnav Achath 73*f767eb91SVaishnav Achath&cdns_csi2rx0 { 74*f767eb91SVaishnav Achath ports { 75*f767eb91SVaishnav Achath #address-cells = <1>; 76*f767eb91SVaishnav Achath #size-cells = <0>; 77*f767eb91SVaishnav Achath 78*f767eb91SVaishnav Achath csi0_port0: port@0 { 79*f767eb91SVaishnav Achath reg = <0>; 80*f767eb91SVaishnav Achath status = "okay"; 81*f767eb91SVaishnav Achath 82*f767eb91SVaishnav Achath csi2rx0_in_sensor: endpoint { 83*f767eb91SVaishnav Achath remote-endpoint = <&csi2_cam0>; 84*f767eb91SVaishnav Achath bus-type = <4>; /* CSI2 DPHY. */ 85*f767eb91SVaishnav Achath clock-lanes = <0>; 86*f767eb91SVaishnav Achath data-lanes = <1 2>; 87*f767eb91SVaishnav Achath }; 88*f767eb91SVaishnav Achath }; 89*f767eb91SVaishnav Achath 90*f767eb91SVaishnav Achath csi0_port1: port@1 { 91*f767eb91SVaishnav Achath reg = <1>; 92*f767eb91SVaishnav Achath status = "disabled"; 93*f767eb91SVaishnav Achath }; 94*f767eb91SVaishnav Achath 95*f767eb91SVaishnav Achath csi0_port2: port@2 { 96*f767eb91SVaishnav Achath reg = <2>; 97*f767eb91SVaishnav Achath status = "disabled"; 98*f767eb91SVaishnav Achath }; 99*f767eb91SVaishnav Achath 100*f767eb91SVaishnav Achath csi0_port3: port@3 { 101*f767eb91SVaishnav Achath reg = <3>; 102*f767eb91SVaishnav Achath status = "disabled"; 103*f767eb91SVaishnav Achath }; 104*f767eb91SVaishnav Achath 105*f767eb91SVaishnav Achath csi0_port4: port@4 { 106*f767eb91SVaishnav Achath reg = <4>; 107*f767eb91SVaishnav Achath status = "disabled"; 108*f767eb91SVaishnav Achath }; 109*f767eb91SVaishnav Achath }; 110*f767eb91SVaishnav Achath}; 111*f767eb91SVaishnav Achath 112*f767eb91SVaishnav Achath&dphy0 { 113*f767eb91SVaishnav Achath status = "okay"; 114*f767eb91SVaishnav Achath}; 115*f767eb91SVaishnav Achath 116*f767eb91SVaishnav Achath&ti_csi2rx0 { 117*f767eb91SVaishnav Achath status = "okay"; 118*f767eb91SVaishnav Achath}; 119*f767eb91SVaishnav Achath 120*f767eb91SVaishnav Achath&cdns_csi2rx1 { 121*f767eb91SVaishnav Achath ports { 122*f767eb91SVaishnav Achath #address-cells = <1>; 123*f767eb91SVaishnav Achath #size-cells = <0>; 124*f767eb91SVaishnav Achath 125*f767eb91SVaishnav Achath csi1_port0: port@0 { 126*f767eb91SVaishnav Achath reg = <0>; 127*f767eb91SVaishnav Achath status = "okay"; 128*f767eb91SVaishnav Achath 129*f767eb91SVaishnav Achath csi2rx1_in_sensor: endpoint { 130*f767eb91SVaishnav Achath remote-endpoint = <&csi2_cam1>; 131*f767eb91SVaishnav Achath bus-type = <4>; /* CSI2 DPHY. */ 132*f767eb91SVaishnav Achath clock-lanes = <0>; 133*f767eb91SVaishnav Achath data-lanes = <1 2>; 134*f767eb91SVaishnav Achath }; 135*f767eb91SVaishnav Achath }; 136*f767eb91SVaishnav Achath 137*f767eb91SVaishnav Achath csi1_port1: port@1 { 138*f767eb91SVaishnav Achath reg = <1>; 139*f767eb91SVaishnav Achath status = "disabled"; 140*f767eb91SVaishnav Achath }; 141*f767eb91SVaishnav Achath 142*f767eb91SVaishnav Achath csi1_port2: port@2 { 143*f767eb91SVaishnav Achath reg = <2>; 144*f767eb91SVaishnav Achath status = "disabled"; 145*f767eb91SVaishnav Achath }; 146*f767eb91SVaishnav Achath 147*f767eb91SVaishnav Achath csi1_port3: port@3 { 148*f767eb91SVaishnav Achath reg = <3>; 149*f767eb91SVaishnav Achath status = "disabled"; 150*f767eb91SVaishnav Achath }; 151*f767eb91SVaishnav Achath 152*f767eb91SVaishnav Achath csi1_port4: port@4 { 153*f767eb91SVaishnav Achath reg = <4>; 154*f767eb91SVaishnav Achath status = "disabled"; 155*f767eb91SVaishnav Achath }; 156*f767eb91SVaishnav Achath }; 157*f767eb91SVaishnav Achath}; 158*f767eb91SVaishnav Achath 159*f767eb91SVaishnav Achath&dphy1 { 160*f767eb91SVaishnav Achath status = "okay"; 161*f767eb91SVaishnav Achath}; 162*f767eb91SVaishnav Achath 163*f767eb91SVaishnav Achath&ti_csi2rx1 { 164*f767eb91SVaishnav Achath status = "okay"; 165*f767eb91SVaishnav Achath}; 166