35 				 dp->link.cap.lanes == 0x2 ? 0x3 : 0x1);  in hibmc_dp_link_training_configure()
37 				 dp->link.cap.lanes == 0x2 ? 0x1 : 0);  in hibmc_dp_link_training_configure()
44 	buf[1] = DP_LANE_COUNT_ENHANCED_FRAME_EN | dp->link.cap.lanes;  in hibmc_dp_link_training_configure()
47 		drm_dbg_dp(dp->dev, "dp aux write link rate and lanes failed, ret: %d\n", ret);  in hibmc_dp_link_training_configure()
122 	for (i = 0; i < dp->link.cap.lanes; i++)  in hibmc_dp_link_training_cr_pre()
129 	ret = drm_dp_dpcd_write(dp->aux, DP_TRAINING_LANE0_SET, train_set, dp->link.cap.lanes);  in hibmc_dp_link_training_cr_pre()
130 	if (ret != dp->link.cap.lanes) {  in hibmc_dp_link_training_cr_pre()
144 	for (lane = 0; lane < dp->link.cap.lanes; lane++)  in hibmc_dp_link_get_adjust_train()
183 	switch (dp->link.cap.lanes) {  in hibmc_dp_link_reduce_lane()
185 		dp->link.cap.lanes--;  in hibmc_dp_link_reduce_lane()
221 		if (drm_dp_clock_recovery_ok(lane_status, dp->link.cap.lanes)) {  in hibmc_dp_link_training_cr()
240 					dp->link.cap.lanes);  in hibmc_dp_link_training_cr()
241 		if (ret != dp->link.cap.lanes) {  in hibmc_dp_link_training_cr()
274 		if (!drm_dp_clock_recovery_ok(lane_status, dp->link.cap.lanes)) {  in hibmc_dp_link_training_channel_eq()
281 		if (drm_dp_channel_eq_ok(lane_status, dp->link.cap.lanes)) {  in hibmc_dp_link_training_channel_eq()
294 					dp->link.train_set, dp->link.cap.lanes);  in hibmc_dp_link_training_channel_eq()
295 		if (ret != dp->link.cap.lanes) {  in hibmc_dp_link_training_channel_eq()
334 	dp->link.cap.lanes = dp->dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK;  in hibmc_dp_update_caps()
335 	if (dp->link.cap.lanes > HIBMC_DP_LANE_NUM_MAX)  in hibmc_dp_update_caps()
336 		dp->link.cap.lanes = HIBMC_DP_LANE_NUM_MAX;  in hibmc_dp_update_caps()