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Searched +full:k210 +full:- +full:clk (Results 1 – 11 of 11) sorted by relevance

/linux/Documentation/devicetree/bindings/clock/
H A Dcanaan,k210-clk.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/canaan,k210-clk.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Canaan Kendryte K210 Clock
10 - Damien Le Moal <dlemoal@kernel.org>
13 Canaan Kendryte K210 SoC clocks driver bindings. The clock
14 controller node must be defined as a child node of the K210
18 - dt-bindings/clock/k210-clk.h
22 const: canaan,k210-clk
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/linux/drivers/soc/canaan/
H A Dk210-sysctl.c1 // SPDX-License-Identifier: GPL-2.0-or-later
9 #include <linux/clk.h>
12 #include <soc/canaan/k210-sysctl.h>
16 struct device *dev = &pdev->dev; in k210_sysctl_probe()
17 struct clk *pclk; in k210_sysctl_probe()
20 dev_info(dev, "K210 system controller\n"); in k210_sysctl_probe()
43 { .compatible = "canaan,k210-sysctl", },
49 .name = "k210-sysctl",
72 panic("k210-sysctl: ioremap failed"); in k210_soc_early_init()
78 SOC_EARLY_INIT_DECLARE(k210_soc, "canaan,kendryte-k210", k210_soc_early_init);
/linux/arch/riscv/boot/dts/canaan/
H A Dk210.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com>
6 #include <dt-bindings/clock/k210-clk.h>
7 #include <dt-bindings/pinctrl/k210-fpioa.h>
8 #include <dt-bindings/reset/k210-rst.h>
12 * Although the K210 is a 64-bit CPU, the address bus is only 32-bits
15 #address-cells = <1>;
16 #size-cells = <1>;
17 compatible = "canaan,kendryte-k210";
20 * The K210 has an sv39 MMU following the privileged specification v1.9.
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/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dcanaan,k210-sram.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/canaan,k210-sram.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Canaan K210 SRAM memory controller
10 The Canaan K210 SRAM memory controller is responsible for the system's 8 MiB
15 - Conor Dooley <conor@kernel.org>
20 - canaan,k210-sram
25 - description: sram0 clock
26 - description: sram1 clock
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/linux/Documentation/devicetree/bindings/pinctrl/
H A Dcanaan,k210-fpioa.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/canaan,k210-fpioa.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Canaan Kendryte K210 FPIOA
10 - Damien Le Moal <dlemoal@kernel.org>
13 The Canaan Kendryte K210 SoC Fully Programmable IO Array (FPIOA)
16 a per-pin basis.
20 const: canaan,k210-fpioa
29 - description: Controller reference clock source
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/linux/drivers/pinctrl/
H A Dpinctrl-k210.c1 // SPDX-License-Identifier: GPL-2.0-or-later
7 #include <linux/clk.h>
16 #include <linux/pinctrl/pinconf-generic.h>
21 #include <dt-bindings/pinctrl/k210-fpioa.h>
25 #include "pinctrl-utils.h"
28 * The K210 only implements 8 drive levels, even though
54 /* Strong pull up not implemented on K210 */
80 * struct k210_fpioa: Kendryte K210 FPIOA memory mapped registers
81 * @pins: 48 32-bits IO pin registers
130 * no pins 48-55).
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/linux/drivers/clk/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
6 The <linux/clk.h> calls support software clock gating and
16 Select this option when the clock API in <linux/clk.h> is implemented
19 'struct clk'.
29 clk, useful across many platforms, as well as an
30 implementation of the clock API in include/linux/clk.h.
31 Architectures utilizing the common struct clk should select
43 source "drivers/clk/versatile/Kconfig"
59 Low-Noise JESD204B Compliant Clock Jitter Cleaner With Dual Loop PLLs
88 These multi-function devices have two fixed-rate oscillators, clocked at 32KHz each.
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H A Dclk-k210.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com>
6 #define pr_fmt(fmt) "k210-clk: " fmt
15 #include <linux/clk-provider.h>
18 #include <soc/canaan/k210-sysctl.h>
20 #include <dt-bindings/clock/k210-clk.h>
322 * struct k210_sysclk - sysclk driver data
356 pll->id = pllid; in k210_init_pll()
357 pll->reg = regs + k210_plls_cfg[pllid].reg; in k210_init_pll()
358 pll->lock = regs + K210_SYSCTL_PLL_LOCK; in k210_init_pll()
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H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
3 obj-$(CONFIG_HAVE_CLK) += clk-devres.o clk-bulk.o clkdev.o
4 obj-$(CONFIG_COMMON_CLK) += clk.o
5 obj-$(CONFIG_CLK_KUNIT_TEST) += clk-test.o
6 clk-test-y := clk_test.o \
22 obj-$(CONFIG_COMMON_CLK) += clk-divider.o
23 obj-$(CONFIG_COMMON_CLK) += clk-fixed-factor.o
24 obj-$(CONFIG_COMMON_CLK) += clk-fixed-rate.o
25 obj-$(CONFIG_CLK_FIXED_RATE_KUNIT_TEST) += clk-fixed-rate-test.o
26 clk-fixed-rate-test-y := clk-fixed-rate_test.o kunit_clk_fixed_rate_test.dtbo.o
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/linux/drivers/spi/
H A Dspi-dw-mmio.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Memory-mapped interface driver for DW SPI Core
8 #include <linux/clk.h>
24 #include "spi-dw.h"
30 struct clk *clk; member
31 struct clk *pclk;
61 * bit: |---3-------2-------1-------0
79 struct dw_spi *dws = spi_controller_get_devdata(spi->controller); in dw_spi_mscc_set_cs()
81 struct dw_spi_mscc *dwsmscc = dwsmmio->priv; in dw_spi_mscc_set_cs()
90 writel(sw_mode, dwsmscc->spi_mst + MSCC_SPI_MST_SW_MODE); in dw_spi_mscc_set_cs()
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/linux/
H A DMAINTAINERS5 ---------------------------------------------------
21 W: *Web-page* with status/info
23 B: URI for where to file *bugs*. A web-page with detailed bug
28 patches to the given subsystem. This is either an in-tree file,
29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst
46 N: [^a-z]tegra all files whose path contains tegra
64 ----------------
83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS)
85 L: linux-scsi@vger.kernel.org
88 F: drivers/scsi/3w-*
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