Home
last modified time | relevance | path

Searched +full:irqs +full:- +full:reserved (Results 1 – 25 of 365) sorted by relevance

12345678910>>...15

/linux/Documentation/devicetree/bindings/arm/omap/
H A Dcrossbar.txt4 time, so they have to be muxed to the irq-controller appropriately.
10 - compatible : Should be "ti,irq-crossbar"
11 - reg: Base address and the size of the crossbar registers.
12 - interrupt-controller: indicates that this block is an interrupt controller.
13 - ti,max-irqs: Total number of irqs available at the parent interrupt controller.
14 - ti,max-crossbar-sources: Maximum number of crossbar sources that can be routed.
15 - ti,reg-size: Size of a individual register in bytes. Every individual
17 - ti,irqs-reserved: List of the reserved irq lines that are not muxed using
18 crossbar. These interrupt lines are reserved in the soc,
23 - ti,irqs-skip: This is similar to "ti,irqs-reserved", but these are for
[all …]
/linux/drivers/irqchip/
H A Dirq-crossbar.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * drivers/irqchip/irq-crossbar.c
5 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
16 #define IRQ_FREE -1
17 #define IRQ_RESERVED -2
18 #define IRQ_SKIP -3
22 * struct crossbar_device - crossbar device description
47 writel(cb_no, cb->crossbar_base + cb->register_offsets[irq_no]); in crossbar_writel()
52 writew(cb_no, cb->crossbar_base + cb->register_offsets[irq_no]); in crossbar_writew()
57 writeb(cb_no, cb->crossbar_base + cb->register_offsets[irq_no]); in crossbar_writeb()
[all …]
H A Dirq-nvic.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * drivers/irq/irq-nvic.c
5 * Copyright (C) 2008 ARM Limited, All Rights Reserved.
9 * ARMv7-M CPUs (Cortex-M3/M4)
33 * Each bank handles 32 irqs. Only the 16th (= last) bank handles only
34 * 16 irqs.
36 #define NVIC_MAX_IRQ ((NVIC_MAX_BANKS - 1) * 32 + 16)
43 irq_hw_number_t hwirq = (icsr & V7M_SCB_ICSR_VECTACTIVE) - 16; in nvic_handle_irq()
76 unsigned int irqs, i, ret, numbanks; in nvic_of_init() local
85 return -ENOMEM; in nvic_of_init()
[all …]
H A Dirq-pruss-intc.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * PRU-ICSS INTC IRQChip driver for various TI SoCs
5 * Copyright (C) 2016-2020 Texas Instruments Incorporated - http://www.ti.com/
9 * Suman Anna <s-anna@ti.com>
24 * Number of host interrupts reaching the main MPU sub-system. Note that this
57 /* CMR register bit-field macros */
62 /* HMR register bit-field macros */
67 /* HIPIR register bit-fields */
74 * struct pruss_intc_map_record - keeps track of actual mapping state
84 * struct pruss_intc_match_data - match data to handle SoC variations
[all …]
/linux/arch/mips/dec/
H A Dint-handler.S1 /* SPDX-License-Identifier: GPL-2.0 */
12 * Rewritten extensively for controller-driven IRQ support
50 * 3) Linux only thinks in terms of all IRQs on or all IRQs
51 * off, nothing in between like BSD spl() brain-damage.
53 * Furthermore, the IRQs on the DECstations look basically (barring
54 * software IRQs which we don't use at all) like...
59 * -------- ------
72 * -------- ------
77 * 4 Reserved
79 * 6 Reserved
[all …]
/linux/kernel/irq/
H A Dmatrix.c1 // SPDX-License-Identifier: GPL-2.0
41 * irq_alloc_matrix - Allocate a irq_matrix structure and initialize it
58 m->system_map = &m->scratch_map[matrix_size]; in irq_alloc_matrix()
60 m->matrix_bits = matrix_bits; in irq_alloc_matrix()
61 m->alloc_start = alloc_start; in irq_alloc_matrix()
62 m->alloc_end = alloc_end; in irq_alloc_matrix()
63 m->alloc_size = alloc_end - alloc_start; in irq_alloc_matrix()
64 m->maps = __alloc_percpu(struct_size(m->maps, alloc_map, matrix_size * 2), in irq_alloc_matrix()
65 __alignof__(*m->maps)); in irq_alloc_matrix()
66 if (!m->maps) { in irq_alloc_matrix()
[all …]
/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dti,pruss-intc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/ti,pruss-intc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TI PRU-ICSS Local Interrupt Controller
10 - Suman Anna <s-anna@ti.com>
13 Each PRU-ICSS has a single interrupt controller instance that is common
22 The property "ti,irqs-reserved" is used for denoting the connection
30 through 19) are connected to new sub-modules within the ICSSG instances.
32 This interrupt-controller node should be defined as a child node of the
[all …]
/linux/include/linux/mfd/
H A Dintel_soc_pmic_mrfld.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 2019 Intel Corporation. All rights reserved.
50 /* Level 1 IRQs */
60 /* Level 2 IRQs: power button */
64 /* Level 2 IRQs: ADC */
71 /* Level 2 IRQs: charger */
/linux/arch/mips/sgi-ip30/
H A Dip30-irq.c1 // SPDX-License-Identifier: GPL-2.0
3 * ip30-irq.c: Highlevel interrupt handling for IP30 architecture.
18 #include "ip30-common.h"
36 return -ENOSPC; in heart_alloc_int()
50 pending = heart_read(&heart_regs->isr); in ip30_error_irq()
51 mask = heart_read(&heart_regs->imr[cpu]); in ip30_error_irq()
52 cause = heart_read(&heart_regs->cause); in ip30_error_irq()
59 /* Prevent any of the error IRQs from firing again. */ in ip30_error_irq()
60 heart_write(mask & ~(pending), &heart_regs->imr[cpu]); in ip30_error_irq()
62 /* Ack all error IRQs. */ in ip30_error_irq()
[all …]
/linux/drivers/net/ethernet/mellanox/mlx5/core/
H A Dirq_affinity.c1 // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
2 /* Copyright (c) 2021, NVIDIA CORPORATION & AFFILIATES. All rights reserved. */
10 pool->irqs_per_cpu[cpu]--; in cpu_put()
15 pool->irqs_per_cpu[cpu]++; in cpu_get()
18 /* Gets the least loaded CPU. e.g.: the CPU with least IRQs bound to it */
22 int best_cpu = -1; in cpu_get_least_loaded()
26 /* CPU has zero IRQs on it. No need to search any more CPUs. */ in cpu_get_least_loaded()
27 if (!pool->irqs_per_cpu[cpu]) { in cpu_get_least_loaded()
33 if (pool->irqs_per_cpu[cpu] < pool->irqs_per_cpu[best_cpu]) in cpu_get_least_loaded()
36 if (best_cpu == -1) { in cpu_get_least_loaded()
[all …]
H A Dpci_irq.h1 /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */
2 /* Copyright (c) 2021, NVIDIA CORPORATION & AFFILIATES. All rights reserved. */
21 char name[MLX5_MAX_IRQ_NAME - MLX5_MAX_IRQ_IDX_CHARS];
23 struct mutex lock; /* sync IRQs creations */
24 struct xarray irqs; member
33 return !strncmp("mlx5_sf", pool->name, strlen("mlx5_sf")); in mlx5_irq_pool_is_sf_pool()
/linux/arch/arc/include/asm/
H A Dirqflags-arcv2.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com)
12 #define STATUS_AD_BIT 19 /* Disable Align chk: core supports non-aligned */
39 * Linux by default runs at 1, priority 0 reserved for NMI style interrupts
56 * Save IRQ state and disable IRQs
76 * Unconditionally Enable IRQs
89 * Unconditionally Disable IRQs
/linux/drivers/input/serio/
H A Di8042-io.h1 /* SPDX-License-Identifier: GPL-2.0-only */
15 * IRQs.
19 /* defined in include/asm-arm/arch-xxx/irqs.h */
64 * bad things. Because of this the region is always reserved on such boxes. in i8042_platform_init()
68 return -ENODEV; in i8042_platform_init()
72 return -EBUSY; in i8042_platform_init()
/linux/drivers/net/fddi/
H A Ddefza.h1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /* FDDI network adapter driver for DEC FDDIcontroller 700/700-C devices.
36 #define FZA_RESET_CLR 0x0000 /* run self-test and return to work */
43 #define FZA_EVENT_NXM_ERR 0x0080 /* non-existent memory access error;
45 * unsupported partial-word accesses
93 #define FZA_HALT_HOST 0x01 /* host-directed HALT */
95 #define FZA_HALT_NXM 0x03 /* adapter non-existent memory ref. */
102 #define FZA_TEST_FATAL 0x00 /* self-test catastrophic failure */
106 #define FZA_TEST_SRAM_STUCK1 0x04 /* SRAM stuck-at range 1 */
107 #define FZA_TEST_SRAM_STUCK2 0x05 /* SRAM stuck-at range 2 */
[all …]
/linux/arch/alpha/kernel/
H A Dsmc37c669.c32 * All rights reserved.
60 * er 28-Jan-1997 Initial Entry
67 ** Macros for handling device IRQs
69 ** The mask acts as a flag used in mapping actual ISA IRQs (0 - 15)
70 ** to device IRQs (A - H).
84 ** channels to device DMA channels (A - C).
127 ** SMC 37c669 Device IRQs
135 /* SMC37c669_DEVICE_IRQ_G *** RESERVED ***/
218 ** CR00 - default value 0x28
221 ** 0x - 30ua pull-ups on nIDEEN, nHDCS0, NHDCS1
[all …]
/linux/arch/m68k/q40/
H A Dq40ints.c30 * Q40 IRQs are defined as follows:
31 * 3,4,5,6,7,10,11,14,15 : ISA dev IRQs
32 * 16-31: reserved
48 unsigned int irq = data->irq; in q40_irq_startup()
56 /* FIXME return -ENXIO; */ in q40_irq_startup()
98 master_outb(1, EXT_ENABLE_REG); /* ISA IRQ 5-15 */ in q40_init_IRQ()
117 /* simply alternate the ampl (128-SVOL)-(128+SVOL)-..-.. at 200Hz */ in q40_mksound()
137 unsigned char sval=(sound_ticks & 1) ? 128-SVOL : 128+SVOL; in q40_timer_int()
138 sound_ticks--; in q40_timer_int()
163 master_outb(-1, FRAME_CLEAR_REG); in q40_sched_init()
[all …]
/linux/arch/arm/mach-tegra/
H A Dhotplug.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * All Rights Reserved
5 * Copyright (c) 2010, 2012-2013, NVIDIA Corporation. All rights reserved.
34 * platform-specific code to shutdown a CPU
36 * Called with IRQs disabled
/linux/Documentation/arch/x86/i386/
H A DIO-APIC.rst1 .. SPDX-License-Identifier: GPL-2.0
4 IO-APIC
9 Most (all) Intel-MP compliant SMP boards have the so-called 'IO-APIC',
12 IO-APIC, interrupts from hardware will be delivered only to the
16 multiple IO-APICs. Multiple IO-APICs are used in high-end servers to
20 usually worked around by the kernel. If your MP-compliant SMP board does
21 not boot Linux, then consult the linux-smp mailing list archives first.
23 If your box boots fine with enabled IO-APIC IRQs, then your
28 0: 1360293 IO-APIC-edge timer
29 1: 4 IO-APIC-edge keyboard
[all …]
/linux/drivers/mfd/
H A Dtps65090.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
55 .name = "tps65090-pmic",
58 .name = "tps65090-charger",
61 .of_compatible = "ti,tps65090-charger",
66 /* INT1 IRQs*/
88 /* INT2 IRQs*/
125 .irqs = tps65090_irqs,
167 struct tps65090_platform_data *pdata = dev_get_platdata(&client->dev); in tps65090_i2c_probe()
172 if (!pdata && !client->dev.of_node) { in tps65090_i2c_probe()
[all …]
H A Dintel_soc_pmic_bxtwc.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2015-2017, 2022 Intel Corporation. All rights reserved.
155 .irqs = bxtwc_regmap_irqs,
165 .irqs = bxtwc_regmap_irqs_pwrbtn,
175 .irqs = bxtwc_regmap_irqs_tmu,
185 .irqs = bxtwc_regmap_irqs_bcu,
195 .irqs = bxtwc_regmap_irqs_adc,
205 .irqs = bxtwc_regmap_irqs_chgr,
215 .irqs = bxtwc_regmap_irqs_crit,
312 return -EINVAL; in regmap_ipc_byte_reg_read()
[all …]
/linux/drivers/vdpa/solidrun/
H A Dsnet_vdpa.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2022-2023 SolidRun
7 * Author: Alvaro Karsz <alvaro.karsz@solid-run.com>
18 #define SNET_ERR(pdev, fmt, ...) dev_err(&(pdev)->dev, "%s"fmt, "snet_vdpa: ", ##__VA_ARGS__)
19 #define SNET_WARN(pdev, fmt, ...) dev_warn(&(pdev)->dev, "%s"fmt, "snet_vdpa: ", ##__VA_ARGS__)
20 #define SNET_INFO(pdev, fmt, ...) dev_info(&(pdev)->dev, "%s"fmt, "snet_vdpa: ", ##__VA_ARGS__)
21 #define SNET_DBG(pdev, fmt, ...) dev_dbg(&(pdev)->dev, "%s"fmt, "snet_vdpa: ", ##__VA_ARGS__)
22 #define SNET_HAS_FEATURE(s, f) ((s)->negotiated_features & BIT_ULL(f))
24 #define SNET_CFG_VER(snet, ver) ((snet)->psnet->negotiated_cfg_ver >= (ver))
46 /* IRQ index, DPU uses this to parse data from MSI-X table */
[all …]
/linux/arch/sparc/kernel/
H A Dpci_psycho.c1 // SPDX-License-Identifier: GPL-2.0
39 #define PSYCHO_CONTROL_RESV 0x00003ffffffffff0UL /* Reserved */
46 #define PSYCHO_PCICTRL_RESV1 0xfffffff000000000UL /* Reserved */
50 #define PSYCHO_PCICTRL_RESV2 0x00000001ffc00000UL /* Reserved */
52 #define PSYCHO_PCICTRL_RESV3 0x00000000001ff800UL /* Reserved */
56 #define PSYCHO_PCICTRL_RESV4 0x00000000000000c0UL /* Reserved */
93 #define PSYCHO_IOMMU_CTRL_RESV 0xfffffffff9000000UL /* Reserved */
99 #define PSYCHO_IOMMU_TSBSZ_1K 0x0000000000000000UL /* TSB Table 1024 8-byte entries */
100 #define PSYCHO_IOMMU_TSBSZ_2K 0x0000000000010000UL /* TSB Table 2048 8-byte entries */
101 #define PSYCHO_IOMMU_TSBSZ_4K 0x0000000000020000UL /* TSB Table 4096 8-byte entries */
[all …]
/linux/drivers/mailbox/
H A Dstm32-ipcc.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) STMicroelectronics 2018 - All Rights Reserved
55 int irqs[IPCC_IRQ_NUM]; member
85 struct device *dev = ipcc->controller.dev; in stm32_ipcc_rx_irq()
91 proc_offset = ipcc->proc_id ? -IPCC_PROC_OFFST : IPCC_PROC_OFFST; in stm32_ipcc_rx_irq()
92 tosr = readl_relaxed(ipcc->reg_proc + proc_offset + IPCC_XTOYSR); in stm32_ipcc_rx_irq()
93 mr = readl_relaxed(ipcc->reg_proc + IPCC_XMR); in stm32_ipcc_rx_irq()
98 for (chan = 0; chan < ipcc->n_chans; chan++) { in stm32_ipcc_rx_irq()
104 mbox_chan_received_data(&ipcc->controller.chans[chan], NULL); in stm32_ipcc_rx_irq()
106 stm32_ipcc_set_bits(&ipcc->lock, ipcc->reg_proc + IPCC_XSCR, in stm32_ipcc_rx_irq()
[all …]
/linux/drivers/net/wireless/ti/wl12xx/
H A Ddebugfs.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Copyright (C) 2011-2012 Texas Instruments
40 WL12XX_DEBUGFS_FWSTATS_FILE(isr, irqs, "%u");
56 /* skipping wep.reserved */
140 DEBUGFS_FWSTATS_ADD(isr, irqs); in wl12xx_debugfs_add_files()
156 /* skipping wep.reserved */ in wl12xx_debugfs_add_files()
/linux/arch/arm/mach-omap1/
H A Dams-delta-fiq.h1 /* SPDX-License-Identifier: GPL-2.0 */
4 * arch/arm/mach-omap1/ams-delta-fiq.h
19 #include "irqs.h"
23 * IRQ12, described as reserved, has been selected.

12345678910>>...15