| /freebsd/sys/contrib/device-tree/Bindings/arm/omap/ |
| H A D | crossbar.txt | 4 time, so they have to be muxed to the irq-controller appropriately.
10 - compatible : Should be "ti,irq-crossbar"
11 - reg: Base address and the size of the crossbar registers.
12 - interrupt-controller: indicates that this block is an interrupt controller.
13 - ti,max-irqs: Total number of irqs available at the parent interrupt controller.
14 - ti,max-crossbar-sources: Maximum number of crossbar sources that can be routed.
15 - ti,reg-size: Size of a individual register in bytes. Every individual
17 - ti,irqs-reserved: List of the reserved irq lines that are not muxed using
18 crossbar. These interrupt lines are reserved in the soc,
23 - ti,irqs-skip: This is similar to "ti,irqs-reserved", but these are for
[all …]
|
| /freebsd/sys/x86/include/ |
| H A D | intr_machdep.h | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
38 * controller or an MSI interrupt. The 16 ISA IRQs are assigned fixed
42 * the IRQs are not used, so the total number of IRQ values reserved
45 * The first 16 IRQs (0 - 15) are reserved for ISA IRQs. Interrupt
46 * pins on I/O APICs for non-ISA interrupts use IRQ values starting at
101 * An interrupt source. The upper-layer code uses the PIC methods to
102 * control a given source. The lower-layer PIC drivers can store additional
156 int msi_alloc(device_t dev, int count, int maxcount, int *irqs);
159 int msi_release(int *irqs, int count);
|
| /freebsd/tools/tools/pirtool/ |
| H A D | pirtool.c | 2 * SPDX-License-Identifier: BSD-3-Clause
4 * Copyright (c) 2002-2006 Bruce M. Simpson.
5 * All rights reserved
56 void pci_print_irqmask(uint16_t irqs);
58 uint16_t irqs);
67 int err = -1; in main()
68 int mem_fd = -1; in main()
74 while ((ch = getopt(argc, argv, "h")) != -1) in main()
80 argc -= optind; in main()
90 if ((mem_fd = open(_PATH_DEVMEM, O_RDONLY)) == -1) { in main()
[all …]
|
| /freebsd/sys/x86/x86/ |
| H A D | msi.c | 1 /*-
2 * SPDX-License-Identifier: BSD-3-Clause
5 * All rights reserved.
16 * 3. Neither the name of the author nor the names of any co-contributors
93 (MSI_INTEL_ADDR_BASE | (msi)->msi_cpu << 12 | \
96 (MSI_INTEL_DATA_TRGREDG | MSI_INTEL_DATA_DELFIXED | (msi)->msi_vector)
111 * For MSI-X, each message is isolated.
125 bool msi_msix; /* MSI-X message. */
157 "Number of first IRQ reserved for MSI and MSI-X interrupts");
161 "Number of IRQs reserved for MSI and MSI-X interrupts");
[all …]
|
| /freebsd/sys/dev/acpica/ |
| H A D | acpi_container.c | 1 /*-
3 * All rights reserved.
42 int count, int maxcount, int *irqs);
44 int count, int *irqs);
113 int *irqs) in acpi_syscont_alloc_msi() argument
118 irqs)); in acpi_syscont_alloc_msi()
122 acpi_syscont_release_msi(device_t bus, device_t dev, int count, int *irqs) in acpi_syscont_release_msi() argument
126 return (PCIB_RELEASE_MSI(device_get_parent(parent), dev, count, irqs)); in acpi_syscont_release_msi()
|
| /freebsd/sys/i386/pci/ |
| H A D | pci_pir.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
7 * All rights reserved.
81 static void pci_print_irqmask(u_int16_t irqs);
110 /* IRQs 3, 4, 5, 6, 7, 9, 10, 11, 12, 14, 15 */
116 "Mask of allowed irqs to try to route when it has no good clue about\n"
117 "which irqs it should use.");
146 /* XXX - Use pmap_mapdev()? */ in pci_pir_open()
148 if (pt->pt_header.ph_length <= sizeof(struct PIR_header)) in pci_pir_open()
151 i < (pt->pt_header.ph_length); i++) in pci_pir_open()
[all …]
|
| /freebsd/sys/dev/pci/ |
| H A D | pcib_if.m | 1 #-
3 # All rights reserved.
113 # Allocate 'count' MSI messages mapped onto 'count' IRQs. 'irq' points
124 int *irqs;
128 # Release 'count' MSI messages mapped onto 'count' IRQs stored in the
129 # array pointed to by 'irqs'.
135 int *irqs;
139 # Allocate a single MSI-X message mapped onto '*irq'.
148 # Release a single MSI-X message mapped onto 'irq'.
157 # Determine the MSI/MSI-X message address and data for 'irq'. The address
[all …]
|
| /freebsd/sys/arm/arm/ |
| H A D | generic_timer.c | 1 /*-
2 * SPDX-License-Identifier: BSD-3-Clause
6 * All rights reserved.
36 * Cortex-A7, Cortex-A15, ARMv8 and later Generic Timer
113 struct arm_tmr_irq irqs[GT_IRQ_COUNT]; member
131 .name = "sec-phys",
146 .name = "hyp-phys",
151 .name = "hyp-virt",
236 * Read the self-syncronized counter. These cannot be read speculatively so
303 if (arm_tmr_sc->physical_user) { in setup_user_access()
[all …]
|
| /freebsd/sys/powerpc/powernv/ |
| H A D | opal_dev.c | 1 /*-
3 * All rights reserved.
143 pcell_t *irqs; in opaldev_probe() local
146 if (!ofw_bus_is_compatible(dev, "ibm,opal-v3")) in opaldev_probe()
153 /* Manually add IRQs before attaching */ in opaldev_probe()
154 if (OF_hasprop(ofw_bus_get_node(dev), "opal-interrupts")) { in opaldev_probe()
155 iparent = OF_finddevice("/interrupt-controller@0"); in opaldev_probe()
159 "opal-interrupts") / sizeof(*irqs); in opaldev_probe()
160 irqs = malloc(n_irqs * sizeof(*irqs), M_DEVBUF, M_WAITOK); in opaldev_probe()
161 OF_getencprop(ofw_bus_get_node(dev), "opal-interrupts", irqs, in opaldev_probe()
[all …]
|
| /freebsd/sys/powerpc/powerpc/ |
| H A D | intr_machdep.c | 1 /*-
2 * SPDX-License-Identifier: BSD-3-Clause
5 * All rights reserved.
34 /*-
36 * All rights reserved.
93 void *priv; /* PIC-private data */
110 u_int irqs; member
122 static u_int nirqs = 16; /* Allocated IRQS (ISA pre-allocated). */
124 static u_int nirqs = 0; /* Allocated IRQs. */
158 snprintf(intrnames + INTRNAME_LEN * index, INTRNAME_LEN, "%-*s", in intrcnt_setname()
[all …]
|
| H A D | openpic.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
5 * All rights reserved.
63 return (bus_space_read_4(sc->sc_bt, sc->sc_bh, reg)); in openpic_read()
69 bus_space_write_4(sc->sc_bt, sc->sc_bh, reg, val); in openpic_write()
80 sc->sc_dev = dev; in openpic_common_attach()
82 sc->sc_rid = 0; in openpic_common_attach()
83 sc->sc_memr = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->sc_rid, in openpic_common_attach()
86 if (sc->sc_memr == NULL) { in openpic_common_attach()
91 sc->sc_bt = rman_get_bustag(sc->sc_memr); in openpic_common_attach()
[all …]
|
| /freebsd/sys/contrib/dev/athk/ath11k/ |
| H A D | ahb.c | 1 // SPDX-License-Identifier: BSD-3-Clause-Clear
3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
11 #include <linux/dma-mapping.h>
27 { .compatible = "qcom,ipq8074-wifi",
30 { .compatible = "qcom,ipq6018-wifi",
33 { .compatible = "qcom,wcn6750-wifi",
36 { .compatible = "qcom,ipq5018-wifi",
47 "misc-pulse1",
48 "misc-latch",
[all …]
|
| H A D | pcic.c | 1 // SPDX-License-Identifier: BSD-3-Clause-Clear
3 * Copyright (c) 2019-2021 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2022, Qualcomm Innovation Center, Inc. All rights reserved.
13 "mhi-er0",
14 "mhi-er1",
27 "host2wbm-desc-feed",
28 "host2reo-re-injection",
29 "host2reo-command",
30 "host2rxdma-monitor-ring3",
31 "host2rxdma-monitor-ring2",
[all …]
|
| /freebsd/sys/arm64/cavium/ |
| H A D | thunder_pcie_pem_fdt.c | 3 * All rights reserved.
98 if (ofw_bus_is_compatible(dev, "cavium,pci-host-thunder-pem")) { in thunder_pem_fdt_probe()
108 int *irqs) in thunder_pem_fdt_alloc_msi() argument
118 irqs)); in thunder_pem_fdt_alloc_msi()
122 thunder_pem_fdt_release_msi(device_t pci, device_t child, int count, int *irqs) in thunder_pem_fdt_release_msi() argument
131 return (intr_release_msi(pci, child, msi_parent, count, irqs)); in thunder_pem_fdt_release_msi()
|
| /freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/ |
| H A D | ti,pruss-intc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controlle
[all...] |
| /freebsd/sys/contrib/xen/arch-x86/hvm/ |
| H A D | save.h | 3 * be saved along with the domain's memory and device-model state.
53 * - Pre-3.4 didn't have msr_tsc_aux
54 * - Pre-4.7 didn't have fpu_initialised
291 * be able to do the modification in-place. in _hvm_hw_fix_cpu()
293 ucpu->nat.error_code = ucpu->cmp.error_code; in _hvm_hw_fix_cpu()
294 ucpu->nat.pending_event = ucpu->cmp.pending_event; in _hvm_hw_fix_cpu()
295 ucpu->nat.tsc = ucpu->cmp.tsc; in _hvm_hw_fix_cpu()
296 ucpu->nat.msr_tsc_aux = 0; in _hvm_hw_fix_cpu()
299 ucpu->nat.flags = XEN_X86_FPU_INITIALISED; in _hvm_hw_fix_cpu()
321 * Where are we in ICW2-4 initialisation (0 means no init in progress)?
[all …]
|
| /illumos-gate/usr/src/uts/i86pc/io/pci/ |
| H A D | pcihrt.h | 23 * Copyright 2005 Sun Microsystems, Inc. All rights reserved.
28 * pcihrt.h -- PCI Hot-Plug Resource Table
38 struct hrt_hdr { /* PCI Hot-Plug Configuration Resource Table header */
40 uint16_t hrt_avail_imap; /* Bitmap of unused IRQs */
41 uint16_t hrt_used_imap; /* Bitmap of IRQs used by PCI */
42 uchar_t hrt_entry_cnt; /* no. of PCI hot-plug slot entries */
44 uchar_t hrt_resv0; /* reserved */
45 uchar_t hrt_resv1; /* reserved */
46 uchar_t hrt_resv2; /* reserved */
47 uchar_t hrt_resv3; /* reserved */
[all …]
|
| /illumos-gate/usr/src/uts/i86pc/io/psm/ |
| H A D | psm_common.c | 22 * Copyright (c) 2004, 2010, Oracle and/or its affiliates. All rights reserved.
46 * the reserved irq list. When 0 (false), the existing state of the ELCR
48 * is programmed to the proper setting for the type of bus (level-triggered
49 * for PCI, edge-triggered for non-PCI). When non-zero (true), vectors
50 * set to edge-mode will not be used when in PIC-mode. The default value
52 * ACPI-specification regardless of this.
82 * irq_cache_table is a list that serves a two-key cache. It is used
83 * as a pci busid/devid/ipin <-> irq cache and also as a acpi
84 * interrupt lnk <-> irq cache.
105 (void *)(((char *)(p)) + (p)->Length)
[all …]
|
| /freebsd/sys/dev/tws/ |
| H A D | tws.c | 1 /*-
2 * SPDX-License-Identifier: BSD-3-Clause
5 * All rights reserved.
89 int tws_setup_intr(struct tws_softc *sc, int irqs);
113 struct tws_softc *sc = dev->si_drv1; in tws_open()
123 struct tws_softc *sc = dev->si_drv1; in tws_close()
133 struct tws_softc *sc = dev->si_drv1; in tws_read()
143 struct tws_softc *sc = dev->si_drv1; in tws_write()
186 sc->tws_dev = dev; in tws_attach()
187 sc->device_id = pci_get_device(dev); in tws_attach()
[all …]
|
| /freebsd/sys/powerpc/powermac/ |
| H A D | cpcht.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (C) 2008-2010 Nathan Whitehorn
5 * All rights reserved.
81 int count, int maxcount, int *irqs);
83 int count, int *irqs);
163 if (strcmp(compatible, "u3-ht") != 0) in cpcht_probe()
185 sc->pci_sc.sc_quirks = OFW_PCI_QUIRK_RANGES_ON_CHILDREN; in cpcht_attach()
186 sc->sc_populated_slots = 0; in cpcht_attach()
187 sc->sc_data = (vm_offset_t)pmap_mapdev(reg[1], reg[2]); in cpcht_attach()
[all …]
|
| /freebsd/share/man/man9/ |
| H A D | bus_alloc_resource.9 | 1 .\" -*- nroff -*-
5 .\" All rights reserved.
56 This is an easy interface to the resource-management functions.
86 .Bl -item
95 .Bl -tag -width SYS_RES_MEMORY
99 for IRQs
148 .Bl -tag -width RF_SHAREABLE
150 resource has been reserved.
164 cannot share IRQs while
183 .Bd -literal
[all …]
|
| /freebsd/share/man/man4/ |
| H A D | hpet.4 | 2 .\" All rights reserved.
35 .Bd -ragged -offset indent
41 .Bl -ohang
57 .Bd -literal
63 controls how much per-CPU event timers should driver attempt to register.
81 Interrupt can be either edge- or level-triggered.
82 In last case they could be safely shared with PCI IRQs.
85 Other modes (LegacyReplacement and ISA IRQs) require special care to setup,
88 Event timers provided by the driver support both one-shot an periodic modes
92 comparator as separate event timer or group them into one or several per-CPU
|
| /freebsd/sys/arm/ti/ |
| H A D | ti_pruss.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
6 * All rights reserved.
175 { -1, 0, 0 }
177 CTASSERT(TI_PRUSS_HOST_IRQS == nitems(ti_pruss_irq_spec) - 1);
182 struct ctl* irqs; in ti_pruss_irq_open() local
184 sc = dev->si_drv1; in ti_pruss_irq_open()
186 irqs = malloc(sizeof(struct ctl), M_DEVBUF, M_WAITOK); in ti_pruss_irq_open()
187 irqs->cnt = sc->tstamps.ctl.cnt; in ti_pruss_irq_open()
188 irqs->idx = sc->tstamps.ctl.idx; in ti_pruss_irq_open()
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/remoteproc/ |
| H A D | qcom,hexagon-v56.txt | 6 - compatible:
10 "qcom,qcs404-cdsp-pil",
11 "qcom,sdm845-adsp-pil"
13 - reg:
15 Value type: <prop-encoded-array>
18 - interrupts-extended:
20 Value type: <prop-encoded-array>
21 Definition: must list the watchdog, fatal IRQs ready, handover and
22 stop-ack IRQs
24 - interrupt-names:
[all …]
|
| H A D | qcom,wcnss-pil.txt | 6 - compatible:
10 "qcom,riva-pil",
11 "qcom,pronto-v1-pil",
12 "qcom,pronto-v2-pil"
14 - reg:
16 Value type: <prop-encoded-array>
20 - reg-names:
25 - interrupts-extended:
27 Value type: <prop-encoded-array>
28 Definition: must list the watchdog and fatal IRQs and may specify the
[all …]
|