Lines Matching +full:irqs +full:- +full:reserved
32 * All rights reserved.
60 * er 28-Jan-1997 Initial Entry
67 ** Macros for handling device IRQs
69 ** The mask acts as a flag used in mapping actual ISA IRQs (0 - 15)
70 ** to device IRQs (A - H).
84 ** channels to device DMA channels (A - C).
127 ** SMC 37c669 Device IRQs
135 /* SMC37c669_DEVICE_IRQ_G *** RESERVED ***/
218 ** CR00 - default value 0x28
221 ** 0x - 30ua pull-ups on nIDEEN, nHDCS0, NHDCS1
222 ** 11 - IRQ_H available as IRQ output,
224 ** 10 - nIDEEN, nHDCS0, nHDCS1 used to control IDE
247 ** CR01 - default value 0x9C
257 unsigned lock_crx: 1; /* Lock CR00 - CR18 */
262 ** CR02 - default value 0x88
275 ** CR03 - default value 0x78
278 ** ------- ------- ------
284 ** ------- ------- -------
287 ** 1 0 Reserved
297 unsigned drvden : 1; /* 1 = high, 0 - output */
304 ** CR04 - default value 0x00
308 ** 00 - Standard and Bidirectional
309 ** 01 - EPP mode and SPP
310 ** 10 - ECP mode
315 ** 11 - ECP mode and EPP mode
324 ** 00 - Normal
325 ** 01 - PPFD1
326 ** 10 - PPFD2
327 ** 11 - Reserved
339 ** 0 - Use pins IRRX, IRTX
340 ** 1 - Use pins IRRX2, IRTX2
359 ** CR05 - default value 0x00
362 ** 00 - Densel output normal
363 ** 01 - Reserved
364 ** 10 - Densel output 1
365 ** 11 - Densel output 0
372 unsigned fdc_dma_mode : 1; /* 0 = burst, 1 = non-burst */
381 ** CR06 - default value 0xFF
394 ** CR07 - default value 0x00
397 ** 0 - Auto Powerdown disabled (default)
398 ** 1 - Auto Powerdown enabled
417 ** CR08 - default value 0x00
428 ** CR09 - default value 0x00
431 ** 00 - ADRx disabled
432 ** 01 - 1 byte decode A<3:0> = 0000b
433 ** 10 - 8 byte block decode A<3:0> = 0XXXb
434 ** 11 - 16 byte block decode A<3:0> = XXXXb
447 ** CR0A - default value 0x00
458 ** CR0B - default value 0x00
471 ** CR0C - default value 0x00
474 ** 000 - Standard (default)
475 ** 001 - IrDA (HPSIR)
476 ** 010 - Amplitude Shift Keyed IR @500 KHz
477 ** 011 - Reserved
478 ** 1xx - Reserved
494 ** CR0D - default value 0x03
496 ** Device ID Register - read only
506 ** CR0E - default value 0x02
508 ** Device Revision Register - read only
518 ** CR0F - default value 0x00
523 unsigned test0 : 1; /* Reserved - set to 0 */
524 unsigned test1 : 1; /* Reserved - set to 0 */
525 unsigned test2 : 1; /* Reserved - set to 0 */
526 unsigned test3 : 1; /* Reserved - set t0 0 */
527 unsigned test4 : 1; /* Reserved - set to 0 */
528 unsigned test5 : 1; /* Reserved - set t0 0 */
529 unsigned test6 : 1; /* Reserved - set t0 0 */
530 unsigned test7 : 1; /* Reserved - set to 0 */
535 ** CR10 - default value 0x00
550 ** CR11 - default value 0x00
562 ** CR12 - CR1D are reserved registers
566 ** CR1E - default value 0x80
569 ** 00 - GAMECS disabled
570 ** 01 - 1 byte decode ADR<3:0> = 0001b
571 ** 10 - 8 byte block decode ADR<3:0> = 0XXXb
572 ** 11 - 16 byte block decode ADR<3:0> = XXXXb
584 ** CR1F - default value 0x00
587 ** --- --- ------- ------- ----------
590 ** 2/1.6/1 MB 3.5" (3-mode)
596 ** pins - DRVDEN0 and DRVDEN1.
610 ** CR20 - default value 0x3C
613 ** - To disable this decode set Addr<9:8> = 0
614 ** - A<10> = 0, A<3:0> = 0XXXb to access.
626 ** CR21 - default value 0x3C
629 ** - To disable this decode set Addr<9:8> = 0
630 ** - A<10> = 0, A<3:0> = 0XXXb to access.
642 ** CR22 - default value 0x3D
645 ** - To disable this decode set Addr<9:8> = 0
646 ** - A<10> = 0, A<3:0> = 0110b to access.
658 ** CR23 - default value 0x00
661 ** - To disable this decode set Addr<9:8> = 0
662 ** - A<10> = 0 to access.
663 ** - If EPP is enabled, A<2:0> = XXXb to access.
675 ** CR24 - default value 0x00
678 ** - To disable this decode set Addr<9:8> = 0
679 ** - A<10> = 0, A<2:0> = XXXb to access.
691 ** CR25 - default value 0x00
694 ** - To disable this decode set Addr<9:8> = 0
695 ** - A<10> = 0, A<2:0> = XXXb to access.
707 ** CR26 - default value 0x00
711 ** D3 - D0 DMA
712 ** D7 - D4 Selected
713 ** ------- --------
729 ** CR27 - default value 0x00
733 ** D3 - D0 IRQ
734 ** D7 - D4 Selected
735 ** ------- --------
743 ** 0111 Reserved
758 ** CR28 - default value 0x00
762 ** D3 - D0 IRQ
763 ** D7 - D4 Selected
764 ** ------- --------
772 ** 0111 Reserved
792 ** CR29 - default value 0x00
796 ** D3 - D0 IRQ
797 ** D7 - D4 Selected
798 ** ------- --------
806 ** 0111 Reserved
826 ** this we only define 1 alias here - for CR24 - as the serial
832 ** here - for CR21 - as the IDE address register.
894 * All rights reserved.
927 * 28-Jan-1997
931 * er 01-May-1997 Fixed pointer conversion errors in
933 * er 28-Jan-1997 Initial version.
935 *--
984 ** and standard ISA IRQs.
996 { SMC37c669_DEVICE_IRQ_A, -1 },
997 { SMC37c669_DEVICE_IRQ_B, -1 },
1002 { SMC37c669_DEVICE_IRQ_H, -1 },
1003 { -1, -1 } /* End of table */
1013 { SMC37c669_DEVICE_IRQ_A, -1 },
1014 { SMC37c669_DEVICE_IRQ_B, -1 },
1019 { SMC37c669_DEVICE_IRQ_H, -1 },
1020 { -1, -1 } /* End of table */
1047 { SMC37c669_DEVICE_DRQ_C, -1 },
1048 { -1, -1 } /* End of table */
1117 **--
1158 ** file, it should call a platform-specific external routine at this in SMC37c669_detect()
1225 **--
1453 **--
1667 **--
1685 cp->drq = drq; in SMC37c669_configure_device()
1688 cp->irq = irq; in SMC37c669_configure_device()
1691 cp->port1 = port; in SMC37c669_configure_device()
1734 **--
1829 ** copy. Any unused parameters will be set to -1. Any
1833 **--
1848 *drq = cp->drq;
1852 *irq = cp->irq;
1856 *port = cp->port1;
1884 **--
1962 **--
1976 wb( &SMC37c669->index_port, SMC37c669_CONFIG_ON_KEY ); in SMC37c669_config_mode()
1977 wb( &SMC37c669->index_port, SMC37c669_CONFIG_ON_KEY ); in SMC37c669_config_mode()
1981 wb( &SMC37c669->index_port, SMC37c669_CONFIG_OFF_KEY ); in SMC37c669_config_mode()
2006 **--
2011 wb(&SMC37c669->index_port, index); in SMC37c669_read_config()
2012 return rb(&SMC37c669->data_port); in SMC37c669_read_config()
2039 **--
2045 wb( &SMC37c669->index_port, index ); in SMC37c669_write_config()
2046 wb( &SMC37c669->data_port, data ); in SMC37c669_write_config()
2072 **--
2091 ** Get IRQs for serial ports 1 & 2 in SMC37c669_init_local_config()
2122 ** Get IRQs for parallel port and floppy controller in SMC37c669_init_local_config()
2200 **--
2230 ** This function translates IRQs back and forth between ISA
2231 ** IRQs and SMC37c669 device IRQs.
2240 ** Returns the translated IRQ, otherwise, returns -1.
2246 **--
2250 int i, translated_irq = -1; in SMC37c669_xlate_irq()
2256 …for ( i = 0; ( SMC37c669_irq_table[i].device_irq != -1 ) || ( SMC37c669_irq_table[i].isa_irq != -1… in SMC37c669_xlate_irq()
2267 …for ( i = 0; ( SMC37c669_irq_table[i].isa_irq != -1 ) || ( SMC37c669_irq_table[i].device_irq != -1… in SMC37c669_xlate_irq()
2292 ** Returns the translated DMA channel, otherwise, returns -1
2298 **--
2302 int i, translated_drq = -1; in SMC37c669_xlate_drq()
2308 …for ( i = 0; ( SMC37c669_drq_table[i].device_drq != -1 ) || ( SMC37c669_drq_table[i].isa_drq != -1… in SMC37c669_xlate_drq()
2319 …for ( i = 0; ( SMC37c669_drq_table[i].isa_drq != -1 ) || ( SMC37c669_drq_table[i].device_drq != -1… in SMC37c669_xlate_drq()
2335 ip->dva = &smc_ddb;
2336 ip->attr = ATTR$M_WRITE | ATTR$M_READ;
2337 ip->len[0] = 0x30;
2338 ip->misc = 0;
2348 ** Allow multiple readers but only one writer. ip->misc keeps track
2351 ip = fp->ip;
2353 if ( fp->mode & ATTR$M_WRITE ) {
2354 if ( ip->misc ) {
2358 ip->misc++;
2363 *fp->offset = xtoi( info );
2373 ip = fp->ip;
2374 if ( fp->mode & ATTR$M_WRITE ) {
2376 ip->misc--;
2392 ip = fp->ip;
2398 if ( !inrange( *fp->offset, 0, ip->len[0] ) )
2400 *buf++ = SMC37c669_read_config( *fp->offset );
2401 *fp->offset += 1;
2417 ip = fp->ip;
2423 if ( !inrange( *fp->offset, 0, ip->len[0] ) )
2425 SMC37c669_write_config( *fp->offset, *buf );
2426 *fp->offset += 1;
2441 printk("-- CR%02x : %02x\n", i, SMC37c669_read_config(i)); in SMC37c669_dump_registers()
2446 * = SMC_init - SMC37c669 Super I/O controller initialization =
2489 -1 in SMC669_Init()
2498 -1 in SMC669_Init()