| /linux/arch/sparc/kernel/ |
| H A D | iommu.c | 2 /* iommu.c: Generic sparc64 IOMMU support.
15 #include <linux/iommu-helper.h>
17 #include <asm/iommu-common.h>
23 #include <asm/iommu.h>
49 /* Must be invoked under the IOMMU lock. */
52 struct iommu *iommu = container_of(iommu_map_table, struct iommu, tbl); in iommu_flushall() local
53 if (iommu->iommu_flushinv) { in iommu_flushall()
54 iommu_write(iommu->iommu_flushinv, ~(u64)0); in iommu_flushall()
59 tag = iommu->iommu_tags; in iommu_flushall()
66 (void) iommu_read(iommu->write_complete_reg); in iommu_flushall()
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| H A D | iommu-common.c | 3 * IOMMU mmap management and range allocation functions.
4 * Based almost entirely upon the powerpc iommu allocator.
10 #include <linux/iommu-helper.h>
13 #include <asm/iommu-common.h>
19 static inline bool need_flush(struct iommu_map_table *iommu) in need_flush() argument
21 return ((iommu->flags & IOMMU_NEED_FLUSH) != 0); in need_flush()
24 static inline void set_flush(struct iommu_map_table *iommu) in set_flush() argument
26 iommu->flags |= IOMMU_NEED_FLUSH; in set_flush()
29 static inline void clear_flush(struct iommu_map_table *iommu) in clear_flush() argument
31 iommu->flags &= ~IOMMU_NEED_FLUSH; in clear_flush()
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| H A D | pci_sun4v.c | 21 #include <asm/iommu-common.h>
23 #include <asm/iommu.h>
58 unsigned long prot; /* IOMMU page protections */
78 static inline bool iommu_use_atu(struct iommu *iommu, u64 mask) in iommu_use_atu() argument
80 return iommu->atu && mask > DMA_BIT_MASK(32); in iommu_use_atu()
102 if (!iommu_use_atu(pbm->iommu, mask)) { in iommu_batch_flush()
109 pr_err_ratelimited("%s: IOMMU map of [%08lx:%08llx:%lx:%lx:%lx] failed with status %ld\n", in iommu_batch_flush()
119 iotsb_num = pbm->iommu->atu->iotsb->iotsb_num; in iommu_batch_flush()
188 struct iommu *iommu; in dma_4v_alloc_coherent() local
213 iommu = dev->archdata.iommu; in dma_4v_alloc_coherent()
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| /linux/drivers/iommu/ |
| H A D | sun50i-iommu.c | 14 #include <linux/iommu.h>
29 #include "iommu-pages.h"
101 struct iommu_device iommu; member
103 /* Lock to modify the IOMMU registers */
125 struct sun50i_iommu *iommu; member
138 static u32 iommu_read(struct sun50i_iommu *iommu, u32 offset) in iommu_read() argument
140 return readl(iommu->base + offset); in iommu_read()
143 static void iommu_write(struct sun50i_iommu *iommu, u32 offset, u32 value) in iommu_write() argument
145 writel(value, iommu->base + offset); in iommu_write()
149 * The Allwinner H6 IOMMU uses a 2-level page table.
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| H A D | msm_iommu.c | 18 #include <linux/iommu.h>
54 static int __enable_clocks(struct msm_iommu_dev *iommu) in __enable_clocks() argument
58 ret = clk_enable(iommu->pclk); in __enable_clocks()
62 if (iommu->clk) { in __enable_clocks()
63 ret = clk_enable(iommu->clk); in __enable_clocks()
65 clk_disable(iommu->pclk); in __enable_clocks()
71 static void __disable_clocks(struct msm_iommu_dev *iommu) in __disable_clocks() argument
73 if (iommu->clk) in __disable_clocks()
74 clk_disable(iommu->clk); in __disable_clocks()
75 clk_disable(iommu->pclk); in __disable_clocks()
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| H A D | rockchip-iommu.c | 3 * IOMMU API for Rockchip
17 #include <linux/iommu.h>
30 #include "iommu-pages.h"
96 /* list of clocks required by IOMMU */
117 struct iommu_device iommu; member
119 struct iommu_domain *domain; /* domain to which iommu is attached */
123 struct device_link *link; /* runtime PM link from IOMMU to master */
124 struct rk_iommu *iommu; member
144 * The Rockchip rk3288 iommu uses a 2-level page table.
153 * Each iommu device has a MMU_DTE_ADDR register that contains the physical
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| H A D | iommu-sysfs.c | 3 * IOMMU sysfs class support
10 #include <linux/iommu.h>
16 * As devices are added to the IOMMU, we'll add links to the group.
38 .name = "iommu",
50 * Init the struct device for the IOMMU. IOMMU specific attributes can
52 * IOMMU type.
54 int iommu_device_sysfs_add(struct iommu_device *iommu, in iommu_device_sysfs_add() argument
62 iommu->dev = kzalloc_obj(*iommu->dev); in iommu_device_sysfs_add()
63 if (!iommu->dev) in iommu_device_sysfs_add()
66 device_initialize(iommu->dev); in iommu_device_sysfs_add()
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| H A D | omap-iommu.c | 3 * omap iommu: tlb and pagetable primitives
18 #include <linux/iommu.h>
19 #include <linux/omap-iommu.h>
30 #include <linux/platform_data/iommu-omap.h>
33 #include "omap-iommu.h"
57 * @dom: generic iommu domain handle
325 * load_iotlb_entry - Set an iommu tlb entry
326 * @obj: target iommu
327 * @e: an iommu tlb entry info
401 * flush_iotlb_page - Clear an iommu tlb entry
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| /linux/drivers/iommu/amd/ |
| H A D | init.c | 19 #include <linux/amd-iommu.h>
25 #include <asm/iommu.h>
38 #include "../iommu-pages.h"
98 * structure describing one IOMMU in the ACPI table. Typically followed by one
118 * A device entry describing which devices a specific IOMMU translates and
139 * An AMD IOMMU memory definition structure. It defines things like exclusion
235 bool translation_pre_enabled(struct amd_iommu *iommu) in translation_pre_enabled() argument
237 return (iommu->flags & AMD_IOMMU_FLAG_TRANS_PRE_ENABLED); in translation_pre_enabled()
240 static void clear_translation_pre_enabled(struct amd_iommu *iommu) in clear_translation_pre_enabled() argument
242 iommu->flags &= ~AMD_IOMMU_FLAG_TRANS_PRE_ENABLED; in clear_translation_pre_enabled()
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| H A D | ppr.c | 9 #include <linux/amd-iommu.h>
13 #include <asm/iommu.h>
18 #include "../iommu-pages.h"
20 int __init amd_iommu_alloc_ppr_log(struct amd_iommu *iommu) in amd_iommu_alloc_ppr_log() argument
22 iommu->ppr_log = iommu_alloc_4k_pages(iommu, GFP_KERNEL | __GFP_ZERO, in amd_iommu_alloc_ppr_log()
24 return iommu->ppr_log ? 0 : -ENOMEM; in amd_iommu_alloc_ppr_log()
27 void amd_iommu_enable_ppr_log(struct amd_iommu *iommu) in amd_iommu_enable_ppr_log() argument
31 if (iommu->ppr_log == NULL) in amd_iommu_enable_ppr_log()
34 iommu_feature_enable(iommu, CONTROL_PPR_EN); in amd_iommu_enable_ppr_log()
36 entry = iommu_virt_to_phys(iommu->ppr_log); in amd_iommu_enable_ppr_log()
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| H A D | iommu.c | 23 #include <linux/iommu-helper.h>
25 #include <linux/amd-iommu.h>
39 #include <asm/iommu.h>
43 #include <linux/generic_pt/iommu.h>
48 #include "../iommu-pages.h"
67 * AMD IOMMU allows up to 2^16 different protection domains. This is a bitmap
75 static void set_dte_entry(struct amd_iommu *iommu,
84 static void iommu_flush_dte_sync(struct amd_iommu *iommu, u16 devid);
86 static struct iommu_dev_data *find_dev_data(struct amd_iommu *iommu, u16 devid);
91 static void clone_aliases(struct amd_iommu *iommu, struct device *dev);
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| H A D | amd_iommu.h | 10 #include <linux/iommu.h>
21 void amd_iommu_restart_log(struct amd_iommu *iommu, const char *evt_type,
24 void amd_iommu_restart_event_logging(struct amd_iommu *iommu);
25 void amd_iommu_restart_ga_log(struct amd_iommu *iommu);
26 void amd_iommu_restart_ppr_log(struct amd_iommu *iommu);
27 void amd_iommu_set_rlookup_table(struct amd_iommu *iommu, u16 devid);
28 void iommu_feature_enable(struct amd_iommu *iommu, u8 bit);
29 void *__init iommu_alloc_4k_pages(struct amd_iommu *iommu,
67 int amd_iommu_iopf_init(struct amd_iommu *iommu);
68 void amd_iommu_iopf_uninit(struct amd_iommu *iommu);
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| /linux/tools/testing/selftests/vfio/lib/ |
| H A D | iommu.c | 39 .container_path = "/dev/iommu",
44 .container_path = "/dev/iommu",
66 VFIO_FAIL("Unrecognized IOMMU mode: %s\n", iommu_mode); in lookup_iommu_mode()
69 int __iommu_hva2iova(struct iommu *iommu, void *vaddr, iova_t *iova) in __iommu_hva2iova() argument
73 list_for_each_entry(region, &iommu->dma_regions, link) { in __iommu_hva2iova()
89 iova_t iommu_hva2iova(struct iommu *iommu, void *vaddr) in iommu_hva2iova() argument
94 ret = __iommu_hva2iova(iommu, vaddr, &iova); in iommu_hva2iova()
95 VFIO_ASSERT_EQ(ret, 0, "%p is not mapped into the iommu\n", vaddr); in iommu_hva2iova()
100 static int vfio_iommu_map(struct iommu *iommu, struct dma_region *region) in vfio_iommu_map() argument
110 if (ioctl(iommu->container_fd, VFIO_IOMMU_MAP_DMA, &args)) in vfio_iommu_map()
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| /linux/Documentation/devicetree/bindings/iommu/ |
| H A D | riscv,iommu.yaml | 4 $id: http://devicetree.org/schemas/iommu/riscv,iommu.yaml#
7 title: RISC-V IOMMU Architecture Implementation
13 The RISC-V IOMMU provides memory address translation and isolation for
22 Visit https://github.com/riscv-non-isa/riscv-iommu for more details.
24 For information on assigning RISC-V IOMMU to its peripheral devices,
25 see generic IOMMU bindings.
28 # For PCIe IOMMU hardware compatible property should contain the vendor
31 # actually required. For non-PCIe hardware implementations 'riscv,iommu'
37 - qemu,riscv-iommu
38 - const: riscv,iommu
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| H A D | iommu.txt | 5 IOMMU device node:
8 An IOMMU can provide the following services:
19 through the IOMMU and faulting when encountering accesses to unmapped
29 IOMMUs can be single-master or multiple-master. Single-master IOMMU devices
31 master IOMMU devices can translate accesses from more than one master.
33 The device tree node of the IOMMU device's parent bus must contain a valid
35 IOMMU maps to memory. An empty "dma-ranges" property means that there is a
36 1:1 mapping from IOMMU to memory.
40 - #iommu-cells: The number of cells in an IOMMU specifier needed to encode an
43 The meaning of the IOMMU specifier is defined by the device tree binding of
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| H A D | qcom,iommu.yaml | 4 $id: http://devicetree.org/schemas/iommu/qcom,iommu.yaml#
7 title: Qualcomm Technologies legacy IOMMU implementations
14 a similar looking IOMMU, but without access to the global register space
23 - qcom,msm8916-iommu
24 - qcom,msm8917-iommu
25 - qcom,msm8937-iommu
26 - qcom,msm8953-iommu
27 - const: qcom,msm-iommu-v1
30 - qcom,msm8953-iommu
31 - qcom,msm8976-iommu
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| H A D | ti,omap-iommu.txt | 1 OMAP2+ IOMMU
5 "ti,omap2-iommu" for OMAP2/OMAP3 IOMMU instances
6 "ti,omap4-iommu" for OMAP4/OMAP5 IOMMU instances
7 "ti,dra7-dsp-iommu" for DRA7xx DSP IOMMU instances
8 "ti,dra7-iommu" for DRA7xx IOMMU instances
9 - ti,hwmods : Name of the hwmod associated with the IOMMU instance
11 - interrupts : Interrupt specifier for the IOMMU instance
12 - #iommu-cells : Should be 0. OMAP IOMMUs are all "single-master" devices,
16 Documentation/devicetree/bindings/iommu/iommu.txt
21 - ti,iommu-bus-err-back : Indicates the IOMMU instance supports throwing
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| H A D | mediatek,iommu.yaml | 4 $id: http://devicetree.org/schemas/iommu/mediatek,iommu.yaml#
7 title: MediaTek IOMMU Architecture Implementation
77 - mediatek,mt6893-iommu-mm # generation two
81 - mediatek,mt8186-iommu-mm # generation two
82 - mediatek,mt8188-iommu-vdo # generation two
83 - mediatek,mt8188-iommu-vpp # generation two
84 - mediatek,mt8188-iommu-infra # generation two
85 - mediatek,mt8189-iommu-apu # generation two
86 - mediatek,mt8189-iommu-infra # generation two
87 - mediatek,mt8189-iommu-mm # generation two
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| H A D | sprd,iommu.yaml | 5 $id: http://devicetree.org/schemas/iommu/sprd,iommu.yaml#
8 title: Unisoc IOMMU and Multi-media MMU
16 - sprd,iommu-v1
18 "#iommu-cells":
21 Unisoc IOMMUs are all single-master IOMMU devices, therefore no
24 Documentation/devicetree/bindings/iommu/iommu.txt
37 - "#iommu-cells"
43 iommu_disp: iommu@63000800 {
44 compatible = "sprd,iommu-v1";
46 #iommu-cells = <0>;
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| /linux/drivers/iommu/intel/ |
| H A D | dmar.c | 28 #include <linux/iommu.h>
33 #include "iommu.h"
35 #include "../iommu-pages.h"
68 static void free_iommu(struct intel_iommu *iommu);
462 if (dmaru->iommu) in dmar_free_drhd()
463 free_iommu(dmaru->iommu); in dmar_free_drhd()
502 drhd->iommu->node = node; in dmar_parse_one_rhsa()
767 pr_warn("No IOMMU scope found for ANDD enumeration ID %d (%s)\n", in dmar_acpi_insert_dev_scope()
939 x86_init.iommu.iommu_init = intel_iommu_init; in detect_intel_iommu()
950 static void unmap_iommu(struct intel_iommu *iommu) in unmap_iommu() argument
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| /linux/tools/testing/selftests/vfio/lib/include/libvfio/ |
| H A D | iommu.h | 27 struct iommu { struct
35 struct iommu *iommu_init(const char *iommu_mode); argument
36 void iommu_cleanup(struct iommu *iommu);
38 int __iommu_map(struct iommu *iommu, struct dma_region *region);
40 static inline void iommu_map(struct iommu *iommu, struct dma_region *region) in iommu_map() argument
42 VFIO_ASSERT_EQ(__iommu_map(iommu, region), 0); in iommu_map()
45 int __iommu_unmap(struct iommu *iomm
28 modeiommu global() argument
30 iommufdiommu global() argument
47 iommu_unmap(struct iommu * iommu,struct dma_region * region) iommu_unmap() argument
54 iommu_unmap_all(struct iommu * iommu) iommu_unmap_all() argument
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| /linux/Documentation/ABI/testing/ |
| H A D | debugfs-amd-iommu | 1 What: /sys/kernel/debug/iommu/amd/iommu<x>/mmio
6 MMIO register offset for iommu<x>, and the file outputs the corresponding
7 MMIO register value of iommu<x>
11 $ echo "0x18" > /sys/kernel/debug/iommu/amd/iommu00/mmio
12 $ cat /sys/kernel/debug/iommu/amd/iommu00/mmio
18 What: /sys/kernel/debug/iommu/amd/iommu<x>/capability
23 capability register offset for iommu<x>, and the file outputs the
24 corresponding capability register value of iommu<x>.
28 $ echo "0x10" > /sys/kernel/debug/iommu/amd/iommu00/capability
29 $ cat /sys/kernel/debug/iommu/amd/iommu00/capability
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| H A D | debugfs-intel-iommu | 1 What: /sys/kernel/debug/iommu/intel/iommu_regset
5 This file dumps all the register contents for each IOMMU device.
11 $ sudo cat /sys/kernel/debug/iommu/intel/iommu_regset
13 IOMMU: dmar0 Register Base Address: 26be37000
24 IOMMU: dmar1 Register Base Address: fed90000
35 IOMMU: dmar2 Register Base Address: fed91000
46 What: /sys/kernel/debug/iommu/intel/ir_translation_struct
57 $ sudo cat /sys/kernel/debug/iommu/intel/ir_translation_struct
59 Remapped Interrupt supported on IOMMU: dmar0
66 Remapped Interrupt supported on IOMMU: dmar1
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| /linux/arch/sparc/mm/ |
| H A D | iommu.c | 3 * iommu.c: IOMMU specific routines for memory management.
26 #include <asm/iommu.h>
60 struct iommu_struct *iommu; in sbus_iommu_init() local
67 iommu = kmalloc_obj(struct iommu_struct); in sbus_iommu_init()
68 if (!iommu) { in sbus_iommu_init()
69 prom_printf("Unable to allocate iommu structure\n"); in sbus_iommu_init()
73 iommu->regs = of_ioremap(&op->resource[0], 0, PAGE_SIZE * 3, in sbus_iommu_init()
75 if (!iommu->regs) { in sbus_iommu_init()
76 prom_printf("Cannot map IOMMU registers\n"); in sbus_iommu_init()
80 control = sbus_readl(&iommu->regs->control); in sbus_iommu_init()
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| /linux/Documentation/devicetree/bindings/virtio/ |
| H A D | pci-iommu.yaml | 4 $id: http://devicetree.org/schemas/virtio/pci-iommu.yaml#
7 title: virtio-iommu device using the virtio-pci transport
13 When virtio-iommu uses the PCI transport, its programming interface is
15 device tree statically describes the relation between IOMMU and DMA
16 masters. Therefore, the PCI root complex that hosts the virtio-iommu
17 contains a child node representing the IOMMU device explicitly.
19 DMA from the IOMMU device isn't managed by another IOMMU. Therefore the
20 virtio-iommu node doesn't have an "iommus" property, and is omitted from
21 the iommu-map property of the root complex.
33 - const: virtio,pci-iommu
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